Backside TSV Dummy Pad Logic for GaN Die ID Encoding

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Solution Overview

Problem

Current GaN RF wafers and shuttle wafers lack die IDs, leading to inefficiencies and errors in production due to the need for handwritten IDs by package foundries, which can be refused and disrupt production cycles.

Innovation Solution

A semiconductor structure with backside through silicon vias (TSVs) and dummy pads, where some pads connect with TSVs and others do not, with a metal coating to define logic states, enabling the generation and reading of die IDs after packaging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If handwritten die IDs are used by package foundry, then die position information can be recorded, but production cycle is extended and errors occur

Engineering Contradiction:
Improvedie position informationVSAvoidproduction cycle
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-defining die ID information through the connection patterns of dummy pads to TSVs during the semiconductor manufacturing process itself, before packaging. The die ID is encoded in the physical structure (connected vs. unconnected dummy pads) rather than being added later by handwriting, thus eliminating the time loss associated with post-manufacturing ID assignment.

Inventive Principle:
Principle #10Preliminary action

2Loss of information

If handwritten die IDs are used by package foundry, then die position information can be recorded, but error rate increases

Engineering Contradiction:
Improvedie position informationVSAvoidaccuracy of die ID
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The patent applies self-service by enabling the semiconductor device itself to carry and present its own die ID information through the connection status of dummy pads to TSVs. Instead of relying on external package foundry to manually assign IDs (which introduces errors), the device structure inherently encodes the die ID, making the system self-sufficient and error-free for die identification.

Inventive Principle:
Principle #25Self-service

3Loss of information

If die IDs are added after packaging, then die position information can be obtained, but production efficiency decreases

Engineering Contradiction:
Improvedie position informationVSAvoidproduction efficiency
Core Design Contradiction:
Loss of informationVSProductivity

Solution Approach 1:

The patent integrates die ID encoding into the preliminary manufacturing stages, where dummy pads are connected or left unconnected to TSVs based on die position. This preliminary encoding eliminates the need for post-packaging ID assignment operations, thereby maintaining high production efficiency while ensuring complete die position information is available.

Inventive Principle:
Principle #10Preliminary action

4Loss of information

If dummy pads are designed to connect with backside TSVs, then die ID can be defined, but device complexity increases

Engineering Contradiction:
Improvedie ID informationVSAvoidsemiconductor structure
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent applies universality by designing dummy pads that serve multiple functions: they can be connected to TSVs for die ID encoding, can be left unconnected for alternative functions, and can serve as both structural elements and information-carrying elements. This multi-functionality allows die ID definition without significantly increasing overall device complexity, as the same structural elements serve dual purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230230930A1Semiconductor structure with backside through silicon vias and method of obtaining die ids thereof
Publication Date: 2023.07.20 UNITED MICROELECTRONICS CORP
  • US20230230930A1 patent drawing
  • US20230230930A1 patent drawing
  • US20230230930A1 patent drawing

AI summary

A semiconductor structure with backside through silicon vias (TSVs) is provided in the present invention, including a semiconductor substrate with a front side and a back side, multiple dummy pads set on the front side, multiple backside TSVs extending from the back side to the front side, wherein a number of the dummy pads are connected with the backside TSVs while other dummy pads are not connected with the backside TSVs, and a metal coating covering the back side and the surface of backside TSVs and connected with those dummy pads that connecting with the backside TSVs.