Backside TSV Sidewall Isolation Liner for MOL Protection

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Solution Overview

Problem

The fabrication of through substrate vias (TSVs) in semiconductor integrated circuits faces challenges with node size scaling below 45 nanometers, as small variations in the TSV process can damage middle of line (MOL) devices, which are on the order of 10 nanometers, while TSVs are on the order of micrometers.

Innovation Solution

A semiconductor wafer with a through substrate via extending through a shallow trench isolation (STI) layer pad and a semiconductor substrate, including a conductive filler material and a sidewall isolation liner layer with different chemical material properties, allowing for controlled etches to expose local interconnects without damaging MOL devices. The method involves etching a TSV cavity, depositing an isolation liner layer, and performing a selective etch to decouple the TSV process from front-side device fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TSV fabrication process is performed, then through substrate vias are created to access active devices, but small variations in the process may damage MOL devices due to size scaling below 45nm

Engineering Contradiction:

ImproveTSV fabrication reliabilityVSAvoiddamage to MOL devices

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a sidewall isolation liner layer as an intermediary protective barrier between the TSV cavity and the MOL devices. This liner layer, deposited on the sidewalls of the TSV cavity, acts as a mediator that prevents direct contact and potential damage between the TSV structure and the sensitive MOL devices during fabrication processes

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The sidewall isolation liner layer is deposited in advance before final TSV processing steps. This preliminary action prepares the TSV structure with protective coverage beforehand, ensuring that subsequent processing steps do not inadvertently damage the MOL devices

Inventive Principle:

Principle #10Preliminary action

2Ease of operation

If TSV cavity is etched through STI layer pad, then access to interconnects is achieved, but selectivity and control during etching becomes challenging

Engineering Contradiction:

Improveaccess to interconnectsVSAvoidetching selectivity

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The sidewall isolation liner layer provides localized protection specifically on the sidewalls of the TSV cavity where it contacts the STI layer pad. This local quality enhancement allows the etching process to proceed with improved selectivity, as the liner material differs from both the STI layer and the underlying substrate, enabling controlled etching through the STI layer to expose interconnects

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables precise exposure of local interconnects within the MOL layer without damaging active devices, improving the selectivity and reducing the impact on MOL interconnect layers during backside TSV formation, thus enhancing the integration of TSVs into advanced CMOS nodes.

Implementation Method 1

depositing an isolation liner layer within the TSV cavity

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

etching through the film on the interconnect/contact and a portion of the isolation liner layer to expose the interconnect/contact

Methodology Applied

Scientific EffectChemical Etching:

Data Source

PatentUS9219032B2Integrating through substrate vias from wafer backside layers of integrated circuits

Publication Date: 2015.12.22 QUALCOMM INC

AI summary

A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed on a contact etch stop layer, separating the ILD layer from the STI layer pad on the surface of the semiconductor substrate. The semiconductor wafer further includes a through substrate via that extends through the STI layer pad and the semiconductor substrate to couple with at least one contact within the ILD layer. The through substrate via includes a conductive filler material and a sidewall isolation liner layer. The sidewall isolation liner layer has a portion that possibly extends into, but not through, the STI layer pad.