Backside Interconnect TSV Structure for Lower Resistance and Capacitance
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Solution Overview
Problem
Existing through vias in semiconductor devices are not entirely satisfactory in reducing resistance and parasitic capacitance, particularly when forming backside interconnect structures that include power rails and signal lines.
Innovation Solution
The development of a through-silicon via (TSV) with a guard ring that includes a combination of frontside and backside features, compatible with semiconductor fabrication processes that involve both frontside and backside interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing through via structures are used in semiconductor devices, then the basic electrical connection is achieved, but the resistance and parasitic capacitance are not sufficiently reduced
Solution Approach 1:
The through via structure is segmented into multiple functional zones: a first portion extending through the first interconnect structure, a second portion extending through the second interconnect structure, and a middle portion connecting them. Each portion can be optimized independently for its specific function, allowing reduction of overall resistance and parasitic capacitance while maintaining reliable electrical connection.
Solution Approach 2:
The patent introduces a vertical dimension to the interconnect structure by creating through via that penetrates through both first and second interconnect structures. This three-dimensional approach allows electrical connections to be established through the substrate thickness, reducing horizontal routing distances and associated parasitic effects.
2Productivity
If backside interconnect structures are formed to improve device performance, then functional density is increased, but the complexity of fabrication processes increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the first interconnect structure on the frontside, bonding to a carrier substrate, thinning and backgrinding to expose the first interconnect structure, forming the second interconnect structure on the backside, and finally forming the through via. This segmentation allows each process stage to be optimized independently while maintaining overall process control.
Solution Approach 2:
The carrier substrate is bonded to the frontside of the device before backside processing. This preliminary action provides mechanical support during subsequent thinning and processing steps, enabling precise formation of the second interconnect structure and through via while maintaining device integrity throughout the complex fabrication sequence.
3Reliability
If through via extends through both first and second interconnect structures, then electrical connection is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The carrier substrate is bonded to the frontside interconnect structure before any backside processing. This preliminary bonding establishes a stable reference plane that enables precise alignment and formation of the through via during subsequent processing steps, reducing the overall manufacturing precision requirements despite the complex multi-structure penetration.
Solution Approach 2:
The through via formation is segmented into forming a first via portion through the first interconnect structure and a second via portion through the second interconnect structure. This segmentation allows each portion to be formed with optimized process parameters and alignment tolerances specific to its location, reducing the cumulative precision requirements compared to forming a single continuous via through all structures.
Data Source
AI summary
A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.