Backside TSV Power Delivery for VLSI Chips With Lower IR Drop
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Solution Overview
Problem
Existing VLSI silicon chip designs face challenges with significant metal routing resources for power and signal connections, leading to IR drop, power loss, limited C4 connections, and complex time convergence due to multiple voltage domains sharing limited wiring resources.
Innovation Solution
The solution involves using through silicon vias (TSVs) and package wire bonds to supply power from the backside of the silicon substrate, utilizing backside metal layers and TSVs to route power closer to the silicon devices, freeing up C4 connections for signal routing, and forming power grids on both front and backside metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal routing resources are used to provide power connections to VLSI chip, then power delivery is achieved, but IR drop and power loss increase
Solution Approach 1:
The patent transitions from planar power routing on the front side to three-dimensional power delivery using TSVs that route power from the back side through the substrate to front-side devices. This vertical dimension addition reduces current path length and resistance, thereby reducing IR drop and power loss while maintaining reliable power delivery
2Reliability
If metal routing resources are used to provide power connections, then power delivery is achieved, but available routing resources for signals are reduced
Solution Approach 1:
The patent segments the routing functions by separating power routing from signal routing. Power connections are routed through dedicated TSVs and back-side metal layers, while signal connections use front-side C4 connections and metal layers. This segmentation allows both power and signal routing to be optimized independently without competing for the same resources
Solution Approach 2:
By moving power routing to the vertical dimension through TSVs and back-side layers, the patent frees up horizontal planar routing resources on the front side for signal connections, thereby increasing the number of available signal routing pathways without compromising power delivery
3Reliability
If multiple voltage domains share limited wiring resources, then power distribution is achieved, but time convergence becomes complex
Solution Approach 1:
The patent segments different voltage domains into separate back-side metal layers and TSV groups, allowing each voltage domain to be independently routed and controlled. This segmentation simplifies timing convergence by reducing electromagnetic interference and crosstalk between different voltage domains while maintaining efficient power distribution
4Productivity
If C4 connections are used for both power and signal routing, then connection density is achieved, but available C4 connections for signals are limited
Solution Approach 1:
The patent segments the connection functions by assigning power routing to TSVs and back-side metal layers while reserving C4 connections exclusively for signal routing. This segmentation maximizes the utilization of C4 connections for signals while power is efficiently delivered through the alternative TSV pathway, thereby increasing overall connection capacity
Solution Approach 2:
By introducing vertical TSV routing as an alternative to planar C4 routing for power connections, the patent increases the effective connection density by utilizing the third dimension, thereby freeing up C4 connections for signal purposes without reducing overall connection capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces IR drop, allows for denser chip module designs, enables wider buses for memory connections, and maintains efficient signal routing without requiring major modifications to the package or heatsink design.
Implementation Method 1
one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate
Data Source
AI summary
An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate.