Backside TSV Reveal with Protective Caps for Uniform Via Exposure
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Solution Overview
Problem
Existing methods for processing the backside of semiconductor elements to expose through-substrate vias (TSVs) are inefficient and prone to damage, particularly due to variations in via depth and width, leading to issues like TSV liner damage, cracking, and non-uniform thinning.
Innovation Solution
The use of protective caps, such as selective and patterned caps, deposited on the backside of TSVs to protect them during substrate thinning and subsequent processing, followed by dielectric layer deposition and planarization to reveal the vias, ensuring uniformity and minimizing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the backside of the semiconductor element is thinned to expose TSVs, then the vias become accessible for bonding, but the TSV liners are damaged and cracking occurs
Solution Approach 1:
A protective cap is deposited over the TSVs before the backside thinning process. This preliminary protective action prevents the TSV liners from damage and cracking during subsequent processing steps, while still allowing the vias to be exposed through the thinned substrate
Solution Approach 2:
The protective cap serves as a cushioning layer that absorbs mechanical stress and prevents cracking in the TSV liners during substrate thinning and handling operations. The cap is specifically designed to provide mechanical support to the vulnerable TSV structures
2Device complexity
If conventional backside processing is used, then the process is simple, but TSV liner damage and stress cracking occur
Solution Approach 1:
The protective cap is deposited as an additional preliminary step before backside thinning. While this adds a processing step, it prevents TSV liner damage and stress cracking, improving overall reliability
Solution Approach 2:
The protective cap acts as an intermediary element between the substrate and the processing environment. It mediates the mechanical stresses during thinning and handling, protecting the TSV liners from damage
3Productivity
If the substrate is thinned without protective measures, then processing is faster, but non-uniform thinning and via damage occur
Solution Approach 1:
The protective cap is deposited before thinning to enable more aggressive and uniform thinning processes. The cap provides a uniform reference surface that facilitates controlled thinning while protecting the underlying TSV structures
Solution Approach 2:
The protective cap allows replacement of mechanical protection methods with a deposited protective layer. This enables more precise control over the thinning process and improves via exposure uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces TSV liner damage and stress cracking, allowing for consistent via exposure and preparation for hybrid bonding, enhancing the reliability and integrity of the semiconductor structure.
Implementation Method 1
The use of protective caps, such as selective and patterned caps, deposited on the backside of TSVs to protect them during substrate thinning and subsequent processing
Implementation Method 2
followed by dielectric layer deposition and planarization to reveal the vias
Data Source
AI summary
Disclosed are methods of microelectronic processing to reveal conductive vias that are at least partially embedded in a bulk semiconductor, and resulting structures. A method of forming a microelectronic structure includes revealing the plurality of conductive vias from a back surface of the bulk semiconductor and forming a protective cap on each of the conductive vias on the back surface of the bulk semiconductor. The protective caps can be patterned or disposed selectively onto the conductive vias. The protective caps can cover the conductive vias or also cover a portion of the bulk semiconductor surrounding the conductive vias. The back surface of the bulk semiconductor is etched to form protruding conductive vias, which can be surrounded by sleeves of the bulk semiconductor. A dielectric layer is deposited over the back surface and planarized to reveal the plurality of conductive vias from the back surface.