Backside TSV Contact Openings with Self-Aligned Spacer Masking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The degradation of insulating liners in through-substrate vias (TSVs) during contact etching leads to loss of lithographic control, insulation failure, and unacceptable electrical behavior, particularly for small diameter TSVs, resulting in reliability issues in 3D semiconductor device structures.
Innovation Solution
The use of a self-aligned spacer layer, either disposable or permanent, to protect the insulating liner on TSV sidewalls and create a mask for forming a contact opening at the bottom of the TSV, thereby preventing degradation and ensuring accurate electrical connection to metal pads in the device layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact etching is performed to create contact openings at the bottom of TSVs, then electrical connection to metal pads is achieved, but the insulating liner degrades leading to loss of lithographic control and insulation failure
Solution Approach 1:
A self-aligned spacer layer is deposited conformally on the sidewalls of the TSV before the contact etching process. This spacer layer is formed in advance to protect the insulating liner during subsequent etching operations, preventing degradation and maintaining lithographic control precision while still allowing electrical connection to be established
2Reliability
If contact etching is performed to establish electrical connection, then conductivity is improved, but insulating liner integrity deteriorates causing insulation failure
Solution Approach 1:
The self-aligned spacer layer acts as an intermediary protective structure between the contact etching process and the insulating liner. It is deposited conformally on the TSV sidewalls and serves as a protective barrier during etching, allowing the etch to proceed without directly attacking the insulating liner, thus maintaining both electrical connection reliability and insulation integrity
3Area of stationary object
If small diameter TSVs are used to reduce device footprint, then device size is reduced, but insulating liner degradation becomes more severe
Solution Approach 1:
The self-aligned spacer layer provides localized protection specifically at the TSV sidewalls where the insulating liner is most vulnerable during contact etching. By applying the protective spacer conformally to the sidewalls, the solution addresses the local quality issue of liner degradation in small diameter TSVs without affecting the overall device footprint reduction achieved by using smaller TSVs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively shields the insulating liner, maintaining its integrity and ensuring reliable electrical connections, thereby enhancing the performance and reliability of 3D semiconductor devices by preventing degradation and ensuring precise lithographic control.
Implementation Method 1
depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV
Implementation Method 2
etching a through-substrate via (TSV) in a substrate from a backside of the substrate
Data Source
AI summary
A method includes etching a through-substrate via (TSV) in a substrate from a backside of the substrate. The substrate has a device layer on a frontside. The method further includes depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV, and etching the spacer layer to form a self-aligned mask for etching a contact opening at the bottom of TSV to a metal pad in the device layer, and etching the contact opening at the bottom of TSV to the metal pad in the device layer. The method further includes disposing a conductive material layer in the TSV and the contact opening to make a vertical interconnection from the backside of the substrate to the metal pad in the device layer.