Semiconductor Package Backside TSV Exposure for Tight Thickness Control
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving precise manufacturing tolerances for chiplet formation due to the downsizing of device dies, which requires tighter control over thickness variations and interconnect structures, especially in advanced technology nodes.
Innovation Solution
The method involves using a front side planarization technique to achieve a total thickness variation of less than 3 μm by flipping and thinning an interposer to expose through-silicon vias, allowing for the mounting of device dies on the backside, and forming interconnect structures using materials like copper and low-k dielectric materials to reduce thickness variation and enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dies are downsized to increase integration density, then component density is improved, but manufacturing precision deteriorates due to tighter thickness variation control requirements
Solution Approach 1:
The substrate is divided into multiple regions with different thicknesses, allowing different portions to be optimized for different functions. The planarization layer is selectively removed in certain regions to expose through-silicon vias while maintaining thickness in other regions, enabling precise local control over thickness variations.
Solution Approach 2:
Different regions of the substrate are given different local properties through selective planarization. Some areas have reduced thickness to expose vias for electrical connections, while other areas maintain original thickness for structural support or additional processing, achieving optimal local characteristics throughout the device.
2Reliability
If through-silicon vias are exposed by thinning the substrate, then electrical connectivity is improved, but manufacturing complexity increases due to additional processing steps
Solution Approach 1:
Through-silicon vias are formed and partially filled with conductive material before the substrate is thinned. This preliminary action ensures that the electrical pathways are established while the substrate still has sufficient thickness for handling and processing, reducing the risk of damage and simplifying subsequent steps.
Solution Approach 2:
A planarization layer is introduced as an intermediary element that protects the through-silicon vias during substrate thinning. This layer is selectively removed only where needed to expose the vias for final electrical connections, mediating between the need for thinning and the need to protect internal structures.
3Productivity
If total thickness variation is reduced to less than 3 μm, then manufacturing yield is improved, but device complexity increases due to advanced planarization requirements
Solution Approach 1:
The substrate thickness is dynamically adjusted across different regions rather than maintaining a uniform thickness. Selective removal of the planarization layer creates a thickness profile that is optimized for each functional region, allowing tight overall thickness control while accommodating local variations needed for via exposure and device operation.
Data Source
AI summary
A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.