Backside-Contact Varactor Layout for Low Parasitic Resistance
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Solution Overview
Problem
Conventional varactor devices face challenges with high parasitic resistance and minimum capacitance due to frontside trench contact and feedthrough vias, which undermine their capacitance ratio and Q factor.
Innovation Solution
The implementation of varactor devices with backside electrical contacts and gate-all-around (GAA) transistor designs, featuring nanoribbon-based architecture and EUV patterning for reduced resistance and enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frontside trench contact and feedthrough vias are used, then electrical connection is achieved, but parasitic resistance increases and Q factor deteriorates
Solution Approach 1:
The patent inverts the conventional contact architecture by moving the electrical contact from the frontside to the backside of the substrate. The backside contact structure includes a contact pad and conductive path formed on the opposite side of the substrate from the varactor device, eliminating the need for frontside trench contacts and feedthrough vias. This inversion removes the parasitic resistance sources while maintaining electrical connection functionality.
Solution Approach 2:
The patent extracts and removes the harmful frontside trench contact and feedthrough via structures from the device architecture. By eliminating these components entirely and replacing them with a backside contact solution, the parasitic resistance elements are taken out of the system, directly improving the Q factor of the varactor device.
2Reliability
If conventional varactor device architecture is used, then device fabrication is simplified, but capacitance ratio is limited by minimum capacitance
Solution Approach 1:
The patent inverts the contact architecture from frontside to backside, which enables the varactor device to achieve lower minimum capacitance values. This architectural inversion allows for improved capacitance ratio performance while the contact structures are integrated into the substrate backend, maintaining fabrication feasibility.
Solution Approach 2:
The backside contact structure is nested within the substrate architecture, with the contact pad and conductive path integrated into the substrate backend. This nesting approach embeds the contact functionality within the existing substrate structure, avoiding additional complex external connections while achieving the desired electrical performance.
3Productivity
If scaling to smaller features is pursued, then device density increases, but performance optimization becomes increasingly difficult
Solution Approach 1:
By inverting the contact architecture to the backside, the patent enables continued scaling of frontside features for higher device density while maintaining optimized electrical performance. The backside contact structures can be scaled independently, allowing both high density and performance optimization to be achieved simultaneously.
Solution Approach 2:
The patent moves the contact functionality to another dimension (the backside of the substrate) rather than competing for space on the frontside. This dimensional separation allows frontside features to be scaled down for increased density while the backside contact structures provide optimized electrical connections, resolving the conflict between density and performance.
Data Source
AI summary
A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other. The additional semiconductor regions may be coupled to two oppositely polarized gates, respectively.