Backside-Emitting VCSEL Layout for High-Density Addressable Arrays
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Solution Overview
Problem
Existing VCSEL devices face challenges in achieving high emitter density and efficient manufacturing due to complex design constraints and inefficient manufacturing processes, particularly in top-emitting configurations that limit VCSEL pitch and increase chip size, and the use of underfill processes complicates small chip manufacturing.
Innovation Solution
A backside emitting VCSEL configuration with distinct layer compositions for emitting and non-emitting structures, allowing anode and cathode contacts on opposite surfaces, enabling reduced pitch and flip-chip bonding, along with dielectric layer deposition and planarization for wafer-level bonding, simplifying manufacturing and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If top-emitting VCSEL configuration is used, then emission is achieved through top surface, but VCSEL pitch is limited and chip size increases
Solution Approach 1:
The patent inverts the traditional top-emitting VCSEL configuration to a backside-emitting configuration. The VCSEL structures now emit light through the substrate backside rather than through the top surface, allowing the top surface to be used for routing contacts and interconnects without blocking emission. This inversion resolves the contradiction by enabling both compact chip size and efficient emission simultaneously.
Solution Approach 2:
The patent changes the emission dimension from vertical (top surface) to horizontal (substrate backside). By routing emission through the substrate backside and using the top surface for electrical connections, the design achieves higher VCSEL pitch and reduced chip size while maintaining emission functionality.
2Quantity of substance
If complex design constraints are imposed to achieve high emitter density, then emitter density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the VCSEL array into emitting VCSEL structures and non-emitting VCSEL structures. The non-emitting structures serve as current return paths and are integrated into the same epitaxial layers, allowing high emitter density without requiring separate complex interconnect structures. This segmentation simplifies the overall design while achieving high density.
Solution Approach 2:
The non-emitting VCSEL structures serve multiple functions: they provide current return paths, maintain structural integrity, and enable addressability. By making these structures multi-functional, the patent achieves high emitter density without proportionally increasing design complexity.
3Ease of manufacture
If underfill process is used for small chip manufacturing, then chip bonding is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary planarization of the top surface before bonding to the driver chip. By creating a planar surface in advance, the need for complex underfill processes is eliminated, simplifying the manufacturing process while still achieving reliable small chip bonding.
Solution Approach 2:
The patent extracts the underfill process from the manufacturing sequence by using preliminary planarization instead. This removal of the underfill step simplifies the manufacturing process while maintaining bonding effectiveness for small chips.
4Device complexity
If distinct layer compositions are used for emitting and non-emitting structures, then current routing is simplified, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the formation of emitting and non-emitting VCSEL structures into a single epitaxial growth process. Both types of structures are created simultaneously in the same epitaxial layers with distinct compositions, simplifying current routing while using standard semiconductor manufacturing techniques that can handle the precision requirements.
Data Source
AI summary
In some implementations, a vertical cavity surface emitting laser (VCSEL) device may include a substrate, and a set of epitaxial layers, disposed on the substrate, defining a plurality of VCSEL mesa structures, where each of the plurality of VCSEL mesa structures has a top surface and a sidewall. The VCSEL device may include an additional layer structure disposed on the set of epitaxial layers, where the additional layer structure configures the plurality of VCSEL mesa structures into a set of emitting VCSEL structures, for backside emission through the substrate, and a set of non-emitting VCSEL structures. The additional layer structure may include a first contact layer on the set of epitaxial layers at a base of the plurality of VCSEL mesa structures and surrounding each of the plurality of VCSEL mesa structures, and a second contact layer on top surfaces of the set of emitting VCSEL structures.