Backside Via Layout for Short- and Long-Channel Semiconductors
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in reducing device defects and improving performance due to increased complexity in manufacturing, particularly in forming backside vias in short-channel and long-channel regions, which affects device density and overall performance.
Innovation Solution
The method involves etching substrates in long-channel regions to form recesses exposing epitaxial source/drain regions while masking short-channel regions, refilling with dielectric materials, and then forming backside vias separately in both regions to reduce depth loading and allow for shorter vias in short-channel regions, thereby improving device performance and increasing density in long-channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside vias are formed in both short-channel and long-channel regions using the same process, then manufacturing simplicity is maintained, but device defects increase and performance deteriorates due to depth loading issues
Solution Approach 1:
The patent divides the substrate into short-channel regions and long-channel regions, and forms backside vias in each region separately through distinct etching and filling processes. This segmentation allows optimization of via depth and formation conditions for each region type, reducing device defects caused by inappropriate via depth while accepting increased manufacturing process complexity.
2Ease of manufacture
If uniform backside vias are formed across all regions, then process simplicity is maintained, but short-channel region performance deteriorates due to excessive via depth
Solution Approach 1:
The patent applies different via formation parameters to different regions: short-channel regions receive shallower vias formed with specific etching conditions, while long-channel regions receive deeper vias. This local quality approach optimizes via depth for each region's specific requirements, improving manufacturing precision and device performance at the cost of increased process complexity.
3Productivity
If feature size is reduced to increase integration density, then device density improves, but manufacturing complexity and defect rates increase
Solution Approach 1:
By segmenting the manufacturing process into region-specific steps for short-channel and long-channel devices, the patent enables precise control of via formation parameters. This allows continued scaling to smaller feature sizes and higher integration densities while managing manufacturing complexity through systematic process division rather than attempting uniform processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces device defects, enables shorter backside vias in short-channel regions, and increases device density in long-channel regions, enhancing overall semiconductor device performance.
Implementation Method 1
etching substrates in long-channel regions to form recesses exposing epitaxial source/drain regions
Implementation Method 2
refilling with dielectric materials
Data Source
AI summary
A semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.