Backside Via Structures for Integrated Circuit Density
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Solution Overview
Problem
There is a challenge in efficiently utilizing the backside of semiconductor wafers for circuit element placement and signal routing, as existing techniques do not allow for flexible and efficient interconnection of circuit elements across different layers, limiting the density and computational resources of integrated circuits.
Innovation Solution
The implementation of an improved via structure on the backside of the wafer that can interconnect circuit elements across non-adjacent layers, enabling flexible routing of both electrical power and signals, and allowing for more efficient use of wafer area by using conductive layers on both the front and back sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional via structures are used on the backside of wafers, then manufacturing is simpler, but circuit density and computational resources are limited
Solution Approach 1:
The patent utilizes the backside of the wafer as an additional dimension for circuit element placement and interconnection. By forming vias and conductive layers on the backside surface, the invention effectively adds a third dimension to traditional planar circuit design, enabling increased circuit density without proportionally increasing footprint area.
Solution Approach 2:
The invention segments the wafer into frontside and backside functional regions, with the backside dedicated to specific circuit elements and interconnections. This segmentation allows independent optimization of each surface's function while maintaining overall system integration, resolving the contradiction between density and complexity.
2Area of stationary object
If the backside of wafers is not utilized for circuit element placement, then manufacturing and design are simpler, but wafer area efficiency is reduced
Solution Approach 1:
The backside of the wafer is designed to serve multiple functions: housing circuit elements, providing interconnection paths, and enabling power distribution. This multi-functionality maximizes the utility of the backside area, improving overall wafer utilization without linearly increasing design complexity.
3Productivity
If circuit elements are placed only on the frontside of wafers, then routing is simpler, but computational resources per unit area are reduced
Solution Approach 1:
The patent introduces backside vias and conductive layers as intermediary structures that facilitate communication between frontside circuit elements and backside circuit elements. These intermediaries enable efficient interconnection across the wafer thickness, increasing computational density while managing complexity through structured intermediate layers.
Data Source
AI summary
An integrated circuit cell is provided, which may include a substrate with a front side and a back side, an active region, a first via, and first, second and third conductive layers. A portion of the active region may be formed within the substrate. The first via and the first, second and third conductive layers are on the back side. The second and third conductive layers may be located further away from the substrate in a first direction than the first and second conductive layers, respectively. The depth of the first via may be greater than a distance between the second conductive layer and the third conductive layer. The integrated circuit cell may include a cell height in a second direction substantially perpendicular to the first direction. A width of the first via along the second direction may be between about 0.05 to about 0.25 times the cell height.