Backside Via Electroplating Using Front-Side Seed Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming conductive vias through substrates face challenges such as difficulty in forming seed layers in high aspect ratio vias, pinch-off during electroplating, and complex seed layer removal, as well as the need for additional processing to connect filled vias to circuit elements.
Innovation Solution
The method involves forming a conductive layer on the front side of the wafer, patterning it to create landing pads, and then electroplating the via material from the backside using the front-side metal interconnects as seed layers and current sources, reducing the need for backside seed layer deposition and subsequent removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conformal seed layer is formed from the backside of the wafer using sputtering, then the seed layer covers the entire surface including high aspect ratio vias, but the deposition process has limitations in forming complete coverage in high aspect ratio vias and requires subsequent material removal
Solution Approach 1:
Instead of forming the seed layer from the backside (conventional approach), the patent forms the seed layer from the frontside of the wafer. This inversion allows the seed layer to be deposited onto planar surfaces where sputtering works effectively, and the electroplating then grows downward through the via to fill it, avoiding the high aspect ratio deposition problem entirely
Solution Approach 2:
The seed layer is formed in advance on the frontside interconnect structures before via formation. This preliminary action ensures that the seed layer is already in place and properly formed on surfaces where deposition is easy, eliminating the need for difficult backside deposition and subsequent removal operations
2Manufacturing precision
If electroplating is performed from the backside of the wafer, then via filling can be achieved, but pinch off occurs near the backside opening resulting in voids in the conductive filler material
Solution Approach 1:
The patent inverts the electroplating direction by performing it from the frontside instead of the backside. The electroplating grows downward from the frontside interconnects through the via, which eliminates the pinch-off effect that occurs when plating from the backside. This directional inversion ensures complete void-free filling of high aspect ratio vias
Solution Approach 2:
By forming the seed layer on the frontside interconnects before via formation, the patent creates a preliminary structure that guides the electroplating growth downward into the via. This preliminary configuration prevents the pinch-off phenomenon by establishing a stable growth front from the beginning of the electroplating process
3Area of stationary object
If the seed layer is formed over the entire surface of the backside of the wafer, then complete via coverage is achieved, but excess material is formed on the wafer surface that must be subsequently removed
Solution Approach 1:
The patent applies local quality by forming the seed layer only on specific frontside interconnect structures and via openings where it is needed, rather than covering the entire backside surface. The electroplating then grows selectively to fill only the via regions, eliminating excess material formation and the need for subsequent removal operations
Solution Approach 2:
By inverting the process to form the seed layer on the frontside instead of the backside, the patent achieves precise local coverage only where needed. The electroplating grows downward from the frontside, filling vias without creating excess material on the wafer surface, thus eliminating the need for material removal
4Length of moving object
If vias are formed through the entire wafer, then through-substrate connections are achieved, but additional processing is required to connect filled vias to circuit elements on the front side
Solution Approach 1:
The patent merges the via filling process with the frontside interconnect structure by using the frontside interconnects themselves as the seed layer and current source for electroplating. This integration eliminates the need for separate connection processing steps, as the via filler grows directly from and connects to the existing frontside circuit elements
Solution Approach 2:
The frontside interconnect structures serve a dual function: they act as both the circuit elements and the seed layer/current source for electroplating. This self-service approach eliminates the need for additional processing to connect vias to circuit elements, as the circuit elements themselves enable the via filling process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient formation of high aspect ratio vias with reduced processing steps, minimized voids, and direct connection to circuit elements, enhancing the build-up rate and reducing excess material removal.
Implementation Method 1
electroplating a conductive via material in the via hole using the landing pad as a seed layer
Data Source
AI summary
A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material.