Backside Via Contact Structure for Low-Leakage GAA FETs
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Solution Overview
Problem
As semiconductor devices are scaled down to sub 20-25 nm technology nodes, the space for backside vias becomes smaller, leading to increased contact resistance and gate current leakage, which affects the performance and efficiency of gate-all-around field effect transistors (GAA FETs).
Innovation Solution
The implementation of an enlarged backside via contact structure in GAA FETs, utilizing materials with different lattice constants and employing advanced lithography and etching processes to form fin structures and nanosheets, reduces contact resistance and minimizes gate current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to sub 20-25 nm technology nodes, then higher device density and performance are achieved, but backside via contact space becomes smaller leading to increased contact resistance and gate current leakage
Solution Approach 1:
The patent transitions from conventional planar via contacts to three-dimensional enlarged via contacts that extend vertically through multiple semiconductor layers. This dimensional change allows the via contact to access a larger surface area of the source/drain region without increasing the lateral footprint, thereby reducing contact resistance while maintaining scaled device dimensions.
Solution Approach 2:
The via contact structure is nested within the stacked semiconductor layer structure, extending through multiple layers to reach the source/drain region. This nested configuration allows the via contact to be integrated within the multi-layer GAA FET architecture, providing electrical connection while maintaining the compact three-dimensional structure.
2Productivity
If device dimensions are scaled down to sub 20-25 nm technology nodes, then higher device density is achieved, but gate current leakage increases
Solution Approach 1:
The patent applies local quality by creating an enlarged via contact structure with specific geometric characteristics (larger surface area, extended depth) localized at the contact region. This localized structural modification reduces contact resistance and minimizes gate current leakage at the via interface without affecting the overall device scaling and other regions of the GAA FET.
3Ease of manufacture
If conventional via contact structure is used in scaled devices, then manufacturing simplicity is maintained, but contact resistance and gate current leakage increase
Solution Approach 1:
The via contact structure is formed preliminarily during the manufacturing process by defining opening(s) through the stacked semiconductor layers before final device assembly. This preliminary formation of the three-dimensional via contact structure integrates the low-resistance contact capability into the standard fabrication sequence, avoiding post-processing complexity while achieving improved electrical performance.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a semiconductor device structure including a gate structure and source/drain regions disposed over a substrate, wherein the source/drain regions are embedded in the semiconductor device structure. An opening is formed in the semiconductor device structure over the source/drain region. A dopant is implanted into sidewalls of the opening. The opening is enlarged over the source/drain region. The source/drain region is exposed. A silicide layer is formed over the exposed source/drain region, and a conductive contact is formed in the opening.