Backside Via Connection Structure for Low-Resistance GAA Nanostructures
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Solution Overview
Problem
Integration of backside interconnect structures with gate-all-around field effect transistors poses a challenge due to the need for patterned structures to be etched through at the level of gate-all-around field effect transistors, leading to high electrical resistance and voltage drop in signal transmission.
Innovation Solution
The development of low resistance connection via structures through device-level structures within a semiconductor nanostructure, such as GAA field effect transistors, which include an alternating stack of silicon-germanium alloy layers and silicon layers, hybrid dielectric fins, and gate template structures to reduce electrical resistance and facilitate efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If patterned structures are etched through gate-all-around field effect transistors to integrate backside interconnect structures, then device density and wiring capability are improved, but electrical resistance increases and voltage drop occurs
Solution Approach 1:
The connection path is divided into multiple segments: frontside contact regions, through-substrate vias, backside contact regions, and interconnect structures. This segmentation allows each component to be optimized independently, reducing overall resistance while maintaining high device density through the distributed via network
Solution Approach 2:
The patent transitions from planar frontside-only interconnection to three-dimensional backside interconnection by forming vias through the substrate thickness dimension. This enables wiring in the vertical dimension, effectively doubling the interconnect available real estate and reducing lateral routing congestion that causes resistance
2Productivity
If through-substrate via structures are formed to connect frontside and backside, then signal transmission capability is improved, but manufacturing complexity increases
Solution Approach 1:
Via holes are formed through the substrate before final interconnect filling, and contact regions are prepared in advance on both frontside and backside. This preliminary structuring simplifies subsequent filling operations and ensures proper alignment, reducing overall manufacturing complexity despite the added three-dimensional connection capability
Solution Approach 2:
The substrate itself acts as an intermediary structure that hosts both frontside devices and backside interconnects. By using the substrate as the mediating element for signal transmission, the patent avoids the need for separate through-silicon via layers, simplifying the overall structure while enabling signal transmission
Data Source
AI summary
A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.