Backside Via Layout in GAA ICs for Dense, Reliable Power Routing
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at increasingly smaller sizes due to the complexity of fabrication processes in the semiconductor integrated circuit (IC) industry, where feature sizes continue to decrease.
Innovation Solution
The use of gate all-around (GAA) transistor structures, patterned using photolithography and self-aligned processes, with semiconductor layers vertically stacked and wrapped by gate structures, and the integration of backside vias and dielectric spacers to facilitate electrical connections and enhance manufacturing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then productivity and cost are improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically stacked channel structures, enabling multiple channels to be stacked vertically. This dimensional change allows functional density to increase without further reducing lateral feature sizes, thereby maintaining manufacturing feasibility while achieving higher device density and performance.
2Quantity of substance
If feature sizes decrease to increase functional density, then more devices fit per chip area, but fabrication reliability deteriorates
Solution Approach 1:
By stacking channels vertically in the third dimension, the patent achieves higher device density without proportionally reducing lateral feature sizes. This approach maintains fabrication reliability by avoiding the extreme miniaturization challenges that would otherwise be required to fit more devices in the same area.
Solution Approach 2:
The patent divides the channel structure into multiple discrete vertically-stacked segments or layers, each with controlled dimensions and properties. This segmentation allows for better control of fabrication processes and defect management, improving overall reliability while achieving high device density.
3Ease of manufacture
If conventional planar structures are used, then manufacturing is simpler, but functional density is limited
Solution Approach 1:
The patent moves from conventional planar 2D structures to three-dimensional vertically stacked channels, enabling multiple functional elements to be integrated within a smaller lateral footprint. This dimensional transition dramatically increases functional density while maintaining compatibility with adapted manufacturing processes.
Solution Approach 2:
The vertically stacked channel structure effectively nests multiple channel layers one above another, similar to nested dolls. This nesting approach maximizes the use of vertical space to achieve higher functional density without requiring proportionally larger lateral dimensions, balancing manufacturing feasibility with performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of reliable semiconductor devices with improved manufacturing efficiency and reduced complexity, allowing for smaller feature sizes and increased functional density in ICs.
Implementation Method 1
patterned using photolithography and self-aligned processes
Data Source
AI summary
A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.