Backside Via Structure With Enlarged Contact Area for GAA RC Delay
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Solution Overview
Problem
As semiconductor devices scale down, the resistance capacitance (RC) time delay increases due to the limited contact area of backside metal vias in gate-all-around (GAA) transistors, degrading device performance.
Innovation Solution
An additional silicon germanium (SiGe) insertion layer is laterally recessed during etching of sacrificial SiGe plugs, increasing the lateral dimension of backside via openings and thus reducing the contact area of backside metal vias, improving RC delay performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the contact area of backside metal vias is reduced due to device scaling, then device density increases, but resistance capacitance time delay increases degrading device performance
Solution Approach 1:
The patent transitions from a planar contact area optimization to a three-dimensional approach by forming backside vias that extend vertically through the substrate. The via structure utilizes the vertical dimension to achieve larger effective contact area with the channel region, compensating for the reduced lateral contact area due to device scaling. This dimensional transition allows maintaining low RC time delay while supporting higher device density.
Solution Approach 2:
The backside via acts as an intermediary conductive structure that bridges the metal interconnect layer and the channel region through the substrate. By introducing this intermediate element with optimized geometry and material properties, the patent achieves improved electrical connection that compensates for the reduced direct contact area, thereby maintaining performance despite scaling-induced area reduction.
2Reliability
If backside via contact area is increased to reduce RC time delay, then device performance improves, but device density decreases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension through substrate-thickness-extending via structures. This allows the contact area to be effectively increased in the vertical direction without consuming additional lateral space, thereby improving RC time delay performance while maintaining high device density in the planar direction.
Solution Approach 2:
The backside via structure is nested within the substrate volume, utilizing the vertical space through the substrate thickness. This nesting approach allows the via to achieve large effective contact area with the channel region without occupying additional lateral footprint, thus improving electrical performance while preserving device density.
Data Source
AI summary
An integrated circuit (IC) structure includes a gate structure, source/drain epitaxial structures, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source/drain epitaxial structures are respectively on opposite sides of the gate structure. The front-side interconnection structure is on front-sides of the source/drain epitaxial structures. The backside dielectric layer is on backsides of the source/drain epitaxial structures. The backside via extends through the backside dielectric layer to one of the source/drain epitaxial structures, and has a maximal lateral dimension larger than a lateral dimension of the source/drain epitaxial structure.