Backside Via Layout in GAA ICs for Lower Resistance Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues in manufacturing integrated circuits with high functional density.
Innovation Solution
The implementation of gate-all-around (GAA) transistor structures, which involve patterning semiconductor layers and gate structures using advanced photolithography and self-aligned processes, such as double-patterning or multi-patterning techniques, to create nanoscale features that enhance device performance and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs lower, but fabrication processes become more difficult and reliability decreases
Solution Approach 1:
The patent applies segmentation by dividing the gate structure formation into multiple discrete steps including forming mandrels, depositing first spacers, forming second spacers, and creating cap structures. This multi-stage self-aligned process enables precise control of nanoscale features while maintaining manufacturing reliability through systematic breakdown of complex fabrication steps
Solution Approach 2:
The patent employs preliminary action through self-aligned processes where mandrels and spacers are formed in advance to define subsequent feature locations. The gate-all-around structures are pre-positioned using sacrificial mandrels that are removed later, ensuring accurate alignment and reducing variability in miniaturized device fabrication
2Area of stationary object
If feature sizes continue to decrease to increase functional density, then chip area utilization improves, but fabrication process complexity increases
Solution Approach 1:
The patent merges multiple patterning operations into a unified self-aligned process where mandrels, spacers, and cap structures are formed in an integrated sequence. The gate-all-around architecture combines source/drain regions, channel, and gate structures into a single cohesive device footprint, maximizing chip area utilization while streamlining fabrication
Solution Approach 2:
The patent implements nesting through the gate-all-around structure where the gate electrode completely surrounds the channel region, and spacers are nested within the gate structure. This nested architecture achieves high functional density and efficient space utilization while maintaining manufacturability through self-aligned formation processes
3Reliability
If advanced photolithography and self-aligned processes are used to create nanoscale features, then device performance enhances, but manufacturing complexity increases
Solution Approach 1:
The patent applies self-service through self-aligned processes where previously formed structures serve as alignment references for subsequent steps. The mandrels and spacers automatically define the positions of gate structures without requiring additional alignment operations, reducing manufacturing complexity while achieving nanoscale precision and enhanced device performance
Data Source
AI summary
A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.