Backside Via Isolation Layout for Gate Leakage Prevention
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Solution Overview
Problem
As semiconductor devices scale down, backside vias connecting source/drain features to metal gates face issues with current leakage due to insufficient insulation, leading to potential shorting and performance degradation.
Innovation Solution
The formation of backside vias is enhanced by creating deeper trenches and using interlayer dielectric layers and dielectric caps to increase spacing between vias and metal gates, along with forming backside vias surrounded by an interlayer dielectric layer to prevent leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside vias are formed to connect source/drain features to metal gates, then electrical connection is achieved, but current leakage occurs due to insufficient insulation
Solution Approach 1:
An interlayer dielectric material is introduced as an intermediary substance between the backside via and the metal gate. This dielectric layer acts as a mediator that prevents direct electrical contact and current leakage while allowing the via to maintain its electrical connection function to the source/drain features.
Solution Approach 2:
The solution moves from a two-dimensional planar layout to a three-dimensional vertical structure by forming deeper trenches and adding vertical dielectric layers. This dimensional change allows the via to be isolated in the vertical dimension, preventing lateral current leakage paths while maintaining electrical connectivity.
2Productivity
If spacing between backside vias and metal gates is reduced to improve functional density, then device integration increases, but leakage current risk increases
Solution Approach 1:
By transitioning to three-dimensional trench structures with vertical dielectric walls, the patent achieves isolation in the vertical dimension, allowing horizontal spacing to be reduced while maintaining leakage prevention through the vertical dielectric barrier.
Solution Approach 2:
The structure employs composite materials combining conductive via materials with insulating dielectric materials in a layered configuration. This composite approach allows closely spaced vias to be electrically isolated from gates while maintaining high functional density.
3Object-generated harmful factors
If deeper trenches are formed to increase spacing and prevent leakage, then insulation improves, but manufacturing complexity increases
Solution Approach 1:
The trench formation process is segmented into multiple controlled steps: initial trench formation, partial filling with dielectric material, and selective removal or additional filling. This segmentation allows precise control over trench depth and dielectric placement, managing manufacturing complexity while achieving adequate spacing.
Solution Approach 2:
Dielectric material is deposited and patterned in preliminary steps before final via completion. This preliminary action establishes the insulation structure in advance, simplifying subsequent processing steps and reducing overall manufacturing complexity.
Data Source
AI summary
One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.