Backside Via-to-Gate Signal Routing for Smaller Semiconductor Chips
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Solution Overview
Problem
Current semiconductor technologies face challenges in miniaturization and integrating backside signals effectively, particularly in connecting gate contacts and signal lines through vias to achieve increased performance and reduced power consumption within limited chip sizes.
Innovation Solution
The integration of backside signals is achieved by using vias to connect gate contacts and signal lines, with power elements connected through additional vias, allowing for efficient power delivery and reduced routing congestion, while maintaining the same metallization level for signal lines and power rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional frontside signal integration is used, then routing is straightforward, but chip size increases and performance decreases
Solution Approach 1:
The patent moves signal routing from the traditional frontside (2D planar routing) to the backside of the chip, utilizing the third dimension (vertical stacking) by routing signals through substrate through-holes and backside interconnect layers. This dimensional transition allows signals to bypass congested frontside routing paths, enabling higher performance within reduced chip footprints.
2Productivity
If backside signal integration is implemented, then chip size is reduced and performance increases, but routing complexity increases
Solution Approach 1:
The patent segments the interconnect system into distinct functional layers: frontside power delivery network, substrate through-hole vias, backside signal routing layers, and gate contact connections. This segmentation allows each layer to be optimized independently for its specific function, managing overall routing complexity while enabling backside signal integration benefits.
Solution Approach 2:
The patent introduces intermediary structures including substrate through-holes filled with conductive material, backside interlayer dielectric layers, and via connections that mediate between frontside power elements and backside signal lines. These intermediaries facilitate the complex backside routing by providing structured transition paths between different interconnect domains.
3Use of energy by moving object
If power elements are separated from signal lines, then power delivery efficiency increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes vertical stacking in the third dimension to separate power elements (located on frontside) from signal lines (routed on backside), allowing both to coexist without lateral interference. This vertical separation enables independent optimization of power delivery and signal routing while maintaining manufacturing feasibility through aligned via structures.
Data Source
AI summary
A semiconductor device includes an isolation region and at least one transistor including a gate region, wherein the gate region is disposed on the isolation region. A via is disposed through a portion of the isolation region and on a signal line. A gate contact is disposed on the gate region. The via is connected to the gate contact and the signal line is connected to the gate region through the via and the gate contact.