Backside Via Isolation Trench Etching for Straight Sidewalls

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Solution Overview

Problem

Existing methods for etching trenches in integrated circuits with small epitaxial critical dimensions struggle to maintain a straight sidewall profile, leading to potential damage to adjacent structures and leakage current issues, particularly in back side power rail applications of multi-gate devices like FinFETs and gate-all-around transistors.

Innovation Solution

An improved etch process for forming high aspect ratio Continuous-Poly-On-Diffusion-Edge (CPODE) structures with a straight sidewall profile, utilizing a self-aligned etch process and a passivation layer to minimize damage to adjacent structures, enabling efficient formation of isolation trenches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional etching schemes (PODE, CPODE) are used to scale gate pitch, then device density increases, but etch profile quality deteriorates and leakage current increases

Engineering Contradiction:
Improvedevice densityVSAvoidetch profile quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etching process is divided into multiple selective etching steps with different etchants, each targeting specific materials (silicon, silicon oxide, silicon nitride) at different rates. This segmentation allows precise control over the etch profile and prevents the formation of bowing, enabling high device density while maintaining manufacturing precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes etching parameters by using different etchants with selective etch rates for different materials. By adjusting etch selectivity and using multiple etching steps with controlled conditions, the process achieves the required etch profile for aggressively scaled circuits while preventing leakage current

Inventive Principle:
Principle #35Parameter changes

2Productivity

If gate pitch is reduced to increase device density, then productivity improves, but etch profile control worsens

Engineering Contradiction:
Improvedevice densityVSAvoidetch profile control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etching process is divided into multiple selective etching steps with different etchants, each targeting specific materials (silicon, silicon oxide, silicon nitride) at different rates. This segmentation allows precise control over the etch profile and prevents the formation of bowing, enabling high device density while maintaining manufacturing precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes etching parameters by using different etchants with selective etch rates for different materials. By adjusting etch selectivity and using multiple etching steps with controlled conditions, the process achieves the required etch profile for aggressively scaled circuits while preventing leakage current

Inventive Principle:
Principle #35Parameter changes

3Reliability

If aggressive scaling is implemented for back side power rail application, then device performance improves, but leakage current increases

Engineering Contradiction:
Improvedevice performanceVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes etching parameters by using different etchants with selective etch rates for different materials. By adjusting etch selectivity and using multiple etching steps with controlled conditions, the process achieves the required etch profile for aggressively scaled circuits while preventing leakage current

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent converts the potential harm of aggressive scaling (which could cause leakage) into a benefit by using selective etching to create precise isolation trenches. The controlled removal of materials at specific locations prevents leakage paths while maintaining the aggressive scaling benefits for device performance

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20250364311A1Semiconductor device structure and methods of forming the same
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250364311A1 patent drawing
  • US20250364311A1 patent drawing
  • US20250364311A1 patent drawing

AI summary

A semiconductor device structure is described. The structure includes a fin structure formed on a substrate, a source/drain feature disposed adjacent the fin structure and over the substrate, wherein a top surface of the source/drain feature and a front side of the substrate are substantially co-planar, an isolation trench extending from the front side of the substrate towards a backside of the substrate, and a backside via contact extending from the backside of the substrate towards and in contact with the source/drain feature, wherein the backside via contact and the isolation trench are parallelly arranged and separated from each other by a constant gap along boundaries of the backside via contact and the isolation trench.