Selective Backside Via Liner for Low-Resistance Power Rail Contacts
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Solution Overview
Problem
Conventional integrated circuits (ICs) face increased voltage drop and power consumption due to the scaling down of power rails, which is not adequately addressed by existing semiconductor fabrication methods, particularly in forming power rails and vias on the backside of ICs with reduced resistance.
Innovation Solution
The method involves forming backside power rails and vias on a semiconductor device with a liner layer deposited only on the sidewalls of the via holes, eliminating the need to break through the liner during conductor deposition, thereby reducing damage to source/drain features and increasing the contact area for reduced resistance, and using a self-aligned process to connect backside power rails to source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form backside vias, then via connectivity is achieved, but the liner layer must be broken through causing damage to source/drain features and increased resistance
Solution Approach 1:
The liner layer is selectively deposited on the sidewalls of via holes before conductor deposition, eliminating the need to break through the liner during subsequent processing. This preliminary protective action prevents damage to source/drain features and maintains low resistance contact.
Solution Approach 2:
The liner layer is applied selectively only on the sidewalls of via holes rather than uniformly across all surfaces. This localized deposition preserves the liner where needed for protection while allowing conductor access where required, reducing damage to source/drain features.
2Productivity
If power rails are scaled down to maintain IC size, then device integration is improved, but voltage drop and power consumption increase
Solution Approach 1:
Power rails are formed on the backside of the IC substrate, utilizing the third dimension (substrate thickness) to accommodate additional power distribution pathways. This dimensional transition allows increased gate density on the frontside without compromising power rail performance, as backside power rails provide alternative current paths that reduce voltage drop.
3Manufacturing precision
If liner layer is deposited on bottom of via holes, then complete coverage is achieved, but conductor deposition requires breaking through liner increasing resistance
Solution Approach 1:
The liner layer deposition is made selective to sidewalls only, with intentional omission from the bottom surface of via holes. This localized quality control ensures complete sidewall coverage for protection while maintaining direct conductor contact with source/drain features at the via bottom, minimizing resistance.
Data Source
AI summary
A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.