Selective Backside Via Liner for Low-Resistance Power Rails
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Solution Overview
Problem
As integrated circuits (IC) continue to scale down, the power rails on the backside of ICs experience increased voltage drop and power consumption due to their stacked configuration, necessitating a solution to reduce resistance and improve performance.
Innovation Solution
The implementation of backside power rails and vias on the semiconductor device, where the backside power rails have wider dimensions than the frontside metal tracks, reducing resistance, and a liner layer is deposited on the sidewalls of backside via holes but not on the bottom, preventing damage to source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are placed on the backside of IC in a stacked configuration, then device integration is improved, but voltage drop and power consumption increase due to resistance
Solution Approach 1:
The patent changes the physical parameters of the power rail structure by forming wider power rails on the backside of the IC. This parameter change (increasing width) directly reduces resistance and power consumption while maintaining the stacked configuration benefit for device integration
2Ease of manufacture
If liner layer is deposited on the bottom of backside via holes, then via formation is simplified, but source/drain features are damaged
Solution Approach 1:
The patent applies local quality by depositing the liner layer selectively only on the sidewalls of the backside via holes and intentionally avoiding the bottom surface. This localized deposition protects the source/drain features at the bottom while still providing liner coverage where needed on the sidewalls
3Loss of energy
If backside power rails have wider dimensions, then resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent inverts the conventional approach by forming power rails on the backside of the IC rather than on the frontside. This inversion allows for wider power rail dimensions to be achieved more easily, reducing resistance while the self-aligned nature of the backside formation process keeps manufacturing complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power rail resistance, increases gate density for greater device integration, and minimizes contact resistance by enhancing the source/drain contact area, thereby addressing the challenges of increased voltage drop and power consumption in scaled-down ICs.
Implementation Method 1
a liner layer is deposited on the sidewalls of backside via holes but not on the bottom
Implementation Method 2
a liner layer is deposited on the sidewalls of backside via holes but not on the bottom
Data Source
AI summary
A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap. A backside power rail is included.