Backside Via Contact Liner for Dense FinFET Power Routing
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Solution Overview
Problem
Advanced integrated circuits face challenges with shrinking gate pitch, contact to gate bridge concerns, and issues with backside power rails such as shorting, leakage, routing resistance, alignment margins, layout flexibility, and packing density.
Innovation Solution
A semiconductor structure is developed with backside power rails and a method to form the same, including a backside via feature with a liner acting as an etch stop layer to prevent damage and a front interconnect structure to collectively route power lines, addressing the concerns of alignment and packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If backside power rails are formed without a protection liner layer, then manufacturing process is simpler, but the inner spacer and backside interlayer dielectric layer are damaged during etching
Solution Approach 1:
A protection liner layer is introduced as an intermediary component between the backside via etch process and the underlying inner spacer and interlayer dielectric layer. This liner layer acts as a sacrificial barrier that absorbs the etching action, preventing direct contact and potential damage to the sensitive underlying structures. The liner layer is specifically designed to be etch-resistant during the backside via formation process while being removable in subsequent steps.
2Productivity
If device pitch is shrunk to increase packing density, then more devices can be integrated, but alignment margins are reduced causing manufacturing difficulties
Solution Approach 1:
The patent utilizes the backside of the substrate as an additional dimension for power rail routing, separate from the front side device layer. By forming backside vias that connect to front side contact regions, the power distribution network is extended to a second plane, effectively doubling the available routing space. This dimensional separation allows independent optimization of device pitch on the front side and power rail layout on the back side, eliminating the trade-off between packing density and alignment precision.
3Device complexity
If conventional front-side only power routing is used, then layout is simpler, but routing resistance and layout flexibility are limited
Solution Approach 1:
The power distribution network is segmented into two independent routing systems: front side power rails and backside power rails. Each system can be independently optimized for its specific function. The backside power rails provide additional parallel current paths, reducing overall routing resistance. The segmentation also improves layout flexibility, as power routes can be independently routed on each side without interfering with signal routing or device placement on the opposite side.
Data Source
AI summary
A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.