Backside Via Nano-FET Structure for Reliable Substrate Scaling
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, which affects production efficiency and cost.
Innovation Solution
The method involves forming a multi-layer stack with alternating semiconductor layers of different materials, patterning semiconductor strips, creating isolation structures, forming epitaxial layers, and constructing gate and source/drain structures using advanced photolithography and etching processes to create nano-FETs, allowing for smaller pitches and more complex designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty and device reliability worsen
Solution Approach 1:
The patent introduces backside vias that extend through the substrate from the front surface to the back surface, adding a vertical dimension to the interconnection architecture. This allows electrical connections to be established through the substrate thickness, enabling continued scaling of planar features while maintaining connectivity reliability through the third dimension.
Solution Approach 2:
The patent divides the interconnection path into multiple segments: front-side contacts, epitaxial source/drain structures, backside vias extending through the substrate, and back-side contacts. This segmentation allows each component to be optimized independently for its specific function while maintaining overall system reliability despite reduced feature sizes.
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity worsens
Solution Approach 1:
The patent forms the epitaxial source and drain structures before forming the gate structure, and establishes backside vias through the substrate before final interlayer dielectric deposition. These preliminary actions simplify subsequent processing steps and reduce the overall fabrication complexity despite the advanced device architecture.
Solution Approach 2:
The backside vias serve multiple functions: providing electrical connection through the substrate, enabling back-side contact configuration, and facilitating heat dissipation paths. This multi-functionality reduces the need for additional specialized structures, thereby simplifying the overall fabrication process.
3Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but manufacturing difficulty worsens
Solution Approach 1:
By utilizing the vertical dimension through backside vias that penetrate the substrate, the patent enables manufacturing processes to maintain larger effective feature dimensions in the planar directions while achieving high functional density through the third dimension, thereby reducing manufacturing difficulty.
Solution Approach 2:
The epitaxial source and drain structures serve as intermediary elements between the front-side contacts and the backside vias, providing a robust connection path that simplifies manufacturing by establishing reliable electrical connections through well-controlled epitaxial growth processes rather than requiring direct through-substrate connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of reliable semiconductor devices with enhanced production efficiency and reduced costs by allowing for smaller feature sizes and increased complexity, improving the manufacturing process for semiconductor devices.
Implementation Method 1
an etching process is performed to remove portions of the dielectric layer, the semiconductor strip, and the isolation layer to form via openings that expose the epitaxial source/drain structures
Implementation Method 2
backside vias are formed in the via openings
Data Source
AI summary
A method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.