Backside-Connecting Via Structure Using Nanosheet Spacers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current backside-connecting via fabrication methods in transistors result in high aspect ratios, leading to increased resistance due to voids and small contact areas, which can cause shorts when attempting to widen the trench for improved fill, compromising the semiconductor device's operability.
Innovation Solution
Incorporating nanosheet spacers between the backside-connecting via and neighboring transistors to reduce the aspect ratio, eliminate voids, and increase the contact area with buried power rails, while preventing electrical contact that could cause shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the trench opening is widened to reduce aspect ratio and increase contact area, then via resistance decreases and void formation is reduced, but the backside-connecting via may come into electrical contact with neighboring transistors causing shorts
Solution Approach 1:
The patent introduces a spacer structure as an intermediary element positioned between the backside-connecting via and the neighboring transistor. This spacer acts as a protective mediator that prevents direct electrical contact while allowing the via to maintain sufficient width for low resistance and good metal fill, thus resolving the contradiction between connection reliability and short circuit risk
2Object-affected harmful factors
If the trench opening is kept narrow to prevent shorts, then transistor isolation is maintained, but via resistance increases due to high aspect ratio and small contact area
Solution Approach 1:
The spacer serves as a protective intermediary that enables the via to be wider than it would otherwise be permitted. By positioning the spacer between the via and transistor, the via can achieve lower resistance through increased width and contact area without compromising transistor isolation, thus improving via connection quality while maintaining short circuit prevention
3Reliability
If the trench is deep to reach the buried power rail, then electrical connection is achieved, but void formation increases due to high aspect ratio
Solution Approach 1:
The patent changes the geometric parameters of the via by widening its opening while maintaining its depth to reach the buried power rail. This parameter change reduces the aspect ratio, enabling better metal fill quality and reducing void formation, while the spacer ensures the widened via does not cause shorts to neighboring transistors
Data Source
AI summary
Embodiments are disclosed for a semiconductor device array and a method for fabricating the semiconductor device array. The semiconductor device array includes a backside power distribution network (BSPDN), a buried power rail (BPR) in electrical contact with the BSPDN, a device layer, and a backside-connecting via. The device layer includes a first transistor, a second transistor, a first spacer, and a second spacer. Further, the first transistor is in electrical contact with the first spacer. Additionally, the second transistor is in electrical contact with the second spacer. Also, the first transistor neighbors the second transistor. Further, the backside-connecting via is in electrical contact with the first transistor, the BPR, the first spacer, and the second spacer.