Backside Via Rail Layout for Lower GAA Source Contact Resistance
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Solution Overview
Problem
GAA transistors face unsatisfactory source contact resistance due to backside silicide regions formed at low temperatures, which affect FEOL devices, and there is a need for improved routing space in integrated circuits with a large number of transistors.
Innovation Solution
A backside via rail is electrically coupled to a silicide region in the source epitaxial structure, formed using a front-side source contact, allowing higher temperature processing to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside silicide regions are formed at low temperatures to protect FEOL devices, then device integrity is maintained, but source contact resistance increases
Solution Approach 1:
The patent divides the silicide formation process into two separate stages: first forming a preliminary silicide region at low temperature during FEOL to maintain device integrity, then forming a second silicide region at high temperature during BEOL to reduce contact resistance. This segmentation allows each process to optimize for its specific requirement without compromising the other.
Solution Approach 2:
The patent performs preliminary silicide formation at low temperature during the FEOL process before the final high-temperature silicide formation in BEOL. This preliminary action establishes the basic electrical connection while preserving device integrity, and the subsequent high-temperature process enhances the connection quality without risking device damage.
2Productivity
If more routing space is allocated for power delivery networks, then transistor density increases, but available area for other circuit elements decreases
Solution Approach 1:
The patent moves the via rail from the traditional front-side planar routing layer to the backside of the substrate, utilizing the third dimension (vertical space on the opposite side). This dimensional transition allows power routing to occur in a previously underutilized space, increasing transistor density on the front side without reducing the available area for other circuit elements.
Solution Approach 2:
The patent inverts the conventional routing approach by placing the via rail on the backside of the substrate rather than on the front side. This inversion allows power delivery networks to route through the substrate backside, freeing up front-side area for higher transistor density while maintaining adequate power routing capabilities.
Data Source
AI summary
An IC structure includes a first transistor, a second transistor, a dielectric fin, a dielectric cap, a backside metal structure, and a source/drain contact. The first transistor includes a first channel region, a first gate structure, and first source/drain features disposed on opposite sides of the first gate structure. The second transistor includes a second channel region, a second gate structure, and second source/drain features disposed on opposite sides of the second gate structure. The dielectric fin is disposed between the first and second transistors. The dielectric cap interfaces a backside surface of the dielectric fin. The source/drain contact abuts the dielectric fin and is electrically coupled to a first one of the first source/drain features by way of a silicide layer and electrically coupled to the backside metal rail by way of physical contact established by the source/drain contact and the backside metal rail.