Backside Via Rail Structure for Lower Source Contact Resistance
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Solution Overview
Problem
GAA transistors face unsatisfactory source contact resistance due to backside silicide regions formed at low temperatures to prevent damage to front-end-of-line devices, limiting the effectiveness of backside power rails in integrated circuit structures.
Innovation Solution
A backside via rail is electrically coupled to a silicide region in the source epitaxial structure, with the silicide region formed using front-side source contact processing at higher temperatures, reducing contact resistance between the backside via rail and the front-side silicide region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside silicide regions are formed at low temperatures to protect FEOL devices, then device integrity is maintained, but source contact resistance increases
Solution Approach 1:
The patent divides the silicide formation process into two separate stages: front-side silicide formation at high temperature during FEOL, and backside silicide formation at low temperature during BEOL. This segmentation allows each stage to be optimized independently - front-side for low contact resistance and backside for device protection - thereby resolving the contradiction between maintaining device integrity and reducing contact resistance.
Solution Approach 2:
The front-side source contact silicide is formed preliminarily during the FEOL process at high temperature, establishing a low-resistance contact before the backend processes begin. This preliminary action ensures that the critical source contact resistance is minimized before any backend processing that might constrain temperature options occurs later.
2Productivity
If more routing space is allocated for backside power rails, then power delivery is improved, but fabrication complexity increases
Solution Approach 1:
The backside via rail structure serves multiple functions simultaneously: it provides power delivery pathways, acts as an etch stop layer during front-side processing, and serves as a structural support for subsequent bonding operations. This multi-functionality allows improved power delivery without proportionally increasing fabrication complexity, as a single structure accomplishes multiple objectives.
Solution Approach 2:
The via rail material acts as an intermediary layer between the substrate and the backside metal interconnects. It mediates the complex fabrication process by providing a stable platform for etching, a foundation for metal deposition, and a protective barrier during front-side processing, thereby simplifying the overall fabrication sequence despite the added routing space requirement.
Data Source
AI summary
An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.