Backside Via Stack With Selective Liner for Lower Resistance
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling multi-gate transistors to smaller dimensions due to variability and space constraints, leading to increased resistance and reduced performance in backside vias.
Innovation Solution
Implementing backside vias with non-uniform widths, where the bottom region is in direct contact with the substrate and the top region is isolated by a liner, allowing for a wider metal width, which improves vertical resistivity and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulative liner is provided throughout the entire via structure, then electrical isolation is improved, but the cross-sectional area of the via is reduced and resistance increases
Solution Approach 1:
The patent applies local quality by providing the insulative liner only in the upper portion of the via structure where electrical isolation is most critical, while leaving the lower portion without liner to maximize cross-sectional area. This selective placement of the insulative layer resolves the contradiction by providing isolation where needed while preserving conductive area where it matters for current flow.
Solution Approach 2:
The via structure is segmented into distinct regions: an upper portion with insulative liner for electrical isolation and a lower portion without liner for optimal conductivity. This segmentation allows each region to be optimized for its specific function, resolving the contradiction between isolation and conductive area requirements.
2Manufacturing precision
If the via width is increased to reduce resistance, then vertical resistivity is improved, but electrical isolation may be compromised
Solution Approach 1:
The insulative liner is applied locally to the upper portion of the via where electrical isolation is critical, while the lower portion maintains maximum width for optimal vertical resistivity. This localized approach allows the via to achieve both wide dimensions for low resistance and sufficient isolation where adjacent structures require it.
3Ease of manufacture
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but variability limits extension into sub-10 nanometer nodes
Solution Approach 1:
The patent introduces a selectively removed liner approach that creates local quality variations in the via structure. This allows standard fabrication processes to be used while achieving improved device performance through the non-uniform liner distribution, resolving the contradiction between process simplicity and device performance requirements for sub-10 nanometer nodes.
Data Source
AI summary
Embodiments disclosed herein include a via structure and methods of forming the via structure. In an embodiment, the via structure comprises a substrate and an opening through the substrate. In an embodiment, the opening has a first portion and a second portion under the first portion. In an embodiment, the via structure further comprises a lining on sidewalls of the first portion of the opening, and a via filling the opening. In an embodiment, the via has a first region with a first width and a second region with a second width, wherein the first width is smaller than the second width.