Back Side Via Conductors With Maskless Self-Alignment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in semiconductor fabrication is the alignment of conductive vias on the back side of a semiconductor substrate to elements on the circuit side, which becomes increasingly difficult as vias shrink, leading to issues like short circuits and open circuits due to misalignment.

Innovation Solution

A method for fabricating semiconductor components using maskless back side alignment to conductive vias, where terminal portions of the vias form self-aligned conductors, eliminating the need for a photo mask and ensuring precise alignment without the risk of short or open circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photo patterning processes are used to align back side conductors to conductive vias, then the fabrication process can be completed, but alignment precision deteriorates as via size decreases, leading to short circuits and open circuits

Engineering Contradiction:
Improvealignment precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Instead of using a photo mask to define the conductor pattern and then aligning it to the vias, the invention inverts the approach by first forming the conductive vias and then using them as the reference for defining the conductor pattern. This is achieved by depositing conductor material over the entire back surface and then selectively removing material that does not align with the vias, ensuring the vias serve as the alignment reference rather than the conductor pattern serving as the reference for via placement.

Inventive Principle:
Principle #13The other way round (Inversion)

2Length of moving object

If conductive vias are made smaller to meet scaling requirements, then component size is reduced, but alignment difficulty increases making conventional fabrication processes inadequate

Engineering Contradiction:
Improvevia diameterVSAvoidalignment precision
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The invention performs preliminary actions by first forming the conductive vias through the substrate before proceeding to the conductor formation step. The vias are prepared with appropriate sizing and positioning in advance, and their surfaces are conditioned (e.g., through etching or coating) to ensure proper adhesion of the conductor material that will be deposited afterward. This preliminary preparation ensures that when the conductor material is deposited and excess is removed, the remaining conductor portions are precisely aligned with the pre-formed vias.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If photo masks are used with larger openings to facilitate alignment, then alignment tolerance is increased, but the risk of short circuits and open circuits increases

Engineering Contradiction:
Improvealignment easeVSAvoidelectrical connection reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The invention employs a self-aligning mechanism where the conductive vias themselves serve as the reference for conductor placement. After depositing conductor material over the entire back surface, the excess material is removed (e.g., through etching or mechanical means), automatically leaving conductor portions that are precisely aligned with the vias. This self-service alignment mechanism eliminates the need for photo masks and manual alignment procedures, ensuring consistent electrical connection reliability without requiring operator skill or complex alignment equipment.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12347731B2Semiconductor components having conductive vias with aligned back side conductors
Publication Date: 2025.07.01 MICRON TECHNOLOGY INC
  • US12347731B2 patent drawing
  • US12347731B2 patent drawing
  • US12347731B2 patent drawing

AI summary

A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.