Backside Via Layout for Stacked Source-Drain-Gate Connections
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Solution Overview
Problem
Existing methods for electrically connecting source-drain regions of monolithically stacked transistors, such as wrap-around constructions or etching through top side epitaxial regions, result in increased die footprint, strain relaxation, and significant capacitive coupling between gate and source-drain regions, degrading transistor performance.
Innovation Solution
Electrically connecting the source-drain regions from the backside of the transistors, forming a via through the bottom epitaxial region and dielectric isolation material, which reduces capacitive coupling by creating a low resistivity, high contact area contact between stacked devices, allowing for faster switching and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wrap-around constructions or through interstitial isolation regions are used to route metal around source and drain regions, then electrical connection between stacked transistors is achieved, but die footprint increases significantly
Solution Approach 1:
Instead of routing metal around the source and drain regions from the top side, the patent forms vias through the source-drain epitaxial regions from the bottom side of the substrate. This inverted approach allows direct vertical connections through the stacked transistor regions, eliminating the need for wrap-around metal routing and significantly reducing the die footprint while maintaining reliable electrical connection.
Solution Approach 2:
The patent transitions from planar metal routing in the horizontal dimension to vertical via formation in the depth dimension. By etching vias through the epitaxial regions from the substrate bottom and forming contacts in the vertical direction, the invention utilizes the third dimension (depth) to achieve electrical connections that would otherwise require extensive horizontal metal routing, thereby compacting the device layout.
2Reliability
If vias are etched through top side epitaxial regions to connect source-drain regions, then electrical connection is achieved, but strain relaxation and body volume loss occur
Solution Approach 1:
Rather than etching vias through the top side epitaxial regions, the patent inverts the process by forming vias through the epitaxial regions from the bottom side of the substrate. This approach allows the source-drain regions to maintain their top-side integrity and strain characteristics while still achieving electrical connection through the bottom-side via formation and subsequent contact deposition.
3Reliability
If vias are formed to gate and source-drain regions, then electrical connection is achieved, but capacitive coupling between gate and source-drain regions increases significantly
Solution Approach 1:
The patent segments the contact formation process by creating separate via structures for gate contacts and source-drain contacts at different locations and depths. The source-drain contacts are formed through vias in the source-drain epitaxial regions from the bottom side, while gate contacts are formed separately, preventing direct capacitive coupling between gate and source-drain regions that would occur with shared via structures.
Solution Approach 2:
By forming source-drain contacts from the bottom side through epitaxial region vias and gate contacts from the top side through separate via structures, the patent separates the contact paths in the vertical dimension. This spatial separation in three-dimensional space reduces the parasitic capacitive coupling between gate and source-drain regions compared to planar contact arrangements.
Data Source
AI summary
A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.