Backside Via Interconnects for Stacked FET Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in achieving compact, high-quality, and cost-effective vertical semiconductor devices with reduced thermal damage and metal contamination, particularly in forming connections between stacked field effect transistors.
Innovation Solution
A method involving backside processing is employed to form a semiconductor device by etching a trench from the substrate side, connecting source/drain regions to a via through a conductive material, which reduces the need for epitaxial growth and minimizes thermal and contamination risks, allowing for a compact design with reduced vertical distance between transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional frontside processing is used to form interconnects, then manufacturing precision can be maintained, but thermal damage to metal contacts and dielectric layers increases and metal contamination occurs
Solution Approach 1:
The patent inverts the conventional processing sequence by performing trench etching and interconnect formation from the backside of the substrate rather than the frontside. This allows the trench to be etched through the substrate to expose the source/drain region, followed by conductive material deposition, and finally frontside hole etching to complete the via. This inversion eliminates the need for high-temperature epitaxial growth that causes thermal damage and metal contamination while maintaining manufacturing precision.
Solution Approach 2:
The patent segments the interconnect formation process into distinct stages: backside trench etching, conductive material filling, and frontside hole etching. This segmentation allows each step to be optimized independently, with the backside processing avoiding thermal damage to frontside structures and the frontside hole etching completing the via without exposing metal contacts to contamination risks.
2Reliability
If epitaxial growth is used to form lateral interconnects, then electrical connections can be established, but thermal budget constraints increase and manufacturing complexity increases
Solution Approach 1:
The patent replaces the mechanical/thermal process of epitaxial growth with a simpler sequence of etching and material deposition. Instead of using high-temperature epitaxial growth to form lateral interconnects, the invention uses backside trench etching followed by conductive material filling, eliminating the need for complex epitaxial equipment and relaxed thermal budget constraints.
3Volume of moving object
If vertical distance between stacked FETs is reduced for compact design, then device area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
By performing the trench etching from the backside, the patent enables precise control of the trench depth and position relative to the source/drain region without compromising the vertical spacing between stacked FETs. This backside processing approach maintains manufacturing precision while allowing reduced vertical distances for compact device design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of compact, high-quality semiconductor devices with reduced thermal damage and metal contamination, facilitating easier and less costly manufacturing while maintaining low resistance connections.
Implementation Method 1
etching, from a bottom side of the substrate towards the first insulating layer, a trench
Implementation Method 2
etching a hole into the first insulating layer, the hole being laterally spaced apart from the stack of FETs
Implementation Method 3
filling the top part of the trench with electrically conductive material, such that the electrically conductive material of the filled top part of the trench electrically connects the bottom side of the first source/drain region to the bottom endpoint of the via
Data Source
AI summary
A method and a semiconductor device are provided. An example method may include forming a stack of field effect transistors, FETs, on top of a substrate. The method may also include forming a first insulating layer laterally surrounding the stack of FETs and etching a hole into the first insulating layer, the hole extending between a top endpoint and a bottom endpoint. The method may further include filling the hole with electrically conductive material such that the electrically conductive material of the filled hole forms a via. Moreover, the method may include etching, from a bottom side of the substrate towards the first insulating layer, a trench, a top part of the trench comprising both a bottom side of the first source/drain region and the bottom endpoint. The method may also include filling the top part of the trench with electrically conductive material.