Backside Source-Drain Via Layout for Stacked Transistor Coupling Reduction
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Solution Overview
Problem
Existing methods for electrically connecting source-drain regions of monolithically stacked transistors, such as wrap-around constructions or etching through top side epitaxial regions, result in increased die footprint, strain relaxation, and significant capacitive coupling between gate and source-drain regions, degrading transistor performance.
Innovation Solution
Electrically connecting the source-drain regions from the backside of the transistors, forming a via through the bottom epitaxial region and dielectric isolation material, which reduces capacitive coupling by creating a low resistivity, high contact area contact between stacked devices, allowing for faster switching and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wrap-around vias are used to connect source-drain regions, then electrical connection is achieved, but die footprint increases significantly
Solution Approach 1:
The patent inverts the conventional approach by forming vias from the backside of the device rather than from the front. This allows source-drain region connections to be established without requiring wrap-around metal routing, thereby reducing the die footprint while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from planar front-side via formation to three-dimensional backside via formation. By accessing the source-drain regions from the opposite side of the substrate, the design eliminates the need for lateral wrap-around connections, reducing the area occupied by interconnect structures.
2Reliability
If vias are etched through top side epitaxial regions, then source-drain connection is achieved, but strain relaxation and body volume loss occur
Solution Approach 1:
Instead of etching vias through the top side epitaxial regions, the patent forms vias from the backside of the substrate. This approach connects source-drain regions without compromising the structural integrity and strain characteristics of the epitaxial layers on the front side.
3Reliability
If vias are formed to gate and source-drain regions, then electrical connection is achieved, but capacitive coupling between gate and source-drain regions increases significantly
Solution Approach 1:
The patent separates gate and source-drain via formation into different spatial dimensions and sides of the device. Gate vias are formed from the front side while source-drain vias are formed from the backside, physically separating the conductive paths and minimizing parasitic capacitive coupling between these regions.
Solution Approach 2:
The patent segments the via formation process into separate front-side and back-side operations. This segmentation allows independent optimization of gate and source-drain connections, with source-drain vias routed from the backside to minimize overlap and capacitive coupling with front-side gate structures.
Data Source
AI summary
A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.