Backside Vias with Tapered Sidewalls for Reduced Resistance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area, including issues with backside via formation, resistance, and device performance, which existing methods struggle to address effectively.
Innovation Solution
The method involves etching a substrate adjacent to gate structures to form recesses, growing epitaxial materials with specific germanium concentrations, and filling these with dielectric material to form larger backside vias, increasing landing area and reducing resistance, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional backside via formation methods are used, then manufacturing process is simpler, but via size is limited and resistance is high
Solution Approach 1:
The patent segments the backside via formation process into multiple distinct stages: forming recesses in the substrate, growing first epitaxial materials in the recesses, growing second epitaxial materials over the first, selectively removing portions to create vias, and filling with conductive material. This segmentation enables precise control over via dimensions and properties, achieving larger via sizes with lower resistance while maintaining manufacturing feasibility through systematic process breakdown.
Solution Approach 2:
The patent applies preliminary actions by growing epitaxial materials with specific germanium concentrations before via formation. The first epitaxial materials are grown with higher germanium content to facilitate selective removal, while the second epitaxial materials provide structural support. These preliminary material preparations enable subsequent via formation with optimized dimensions and electrical properties, resolving the contradiction between via performance and process complexity.
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but backside via formation becomes more difficult
Solution Approach 1:
The patent applies local quality by creating regions with different germanium concentrations in specific locations. The first epitaxial materials are grown with higher germanium content (20-60%) in the recess regions where vias will be formed, while the second epitaxial materials have lower germanium content (0-20%). This local variation in material composition enables selective removal of via materials while preserving surrounding structures, facilitating via formation at reduced feature sizes and maintaining ease of manufacture through localized material property optimization.
3Reliability
If larger backside vias are formed, then landing area increases and resistance decreases, but manufacturing process becomes more complex
Solution Approach 1:
The patent changes material parameters by controlling germanium concentration in the epitaxial layers. The first epitaxial materials contain 20-60% germanium while the second contain 0-20%, creating distinct material properties that enable selective removal. This parameter change allows formation of larger vias with optimized resistance characteristics through precise control of material composition rather than relying solely on geometric dimensions, resolving the trade-off via electrical performance improvement and process complexity management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the formation of larger backside vias, reduces resistance, and improves device performance by increasing the landing area and decreasing RC time delay, addressing the limitations of existing methods in semiconductor device manufacturing.
Implementation Method 1
forming first epitaxial materials in the first recesses, forming second epitaxial materials over the first epitaxial materials
Data Source
AI summary
Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.