Backside Via Width Variation for Power Rail Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity of fabrication processes as feature sizes decrease, making it difficult to maintain device reliability and efficiency.
Innovation Solution
The implementation of gate-all-around (GAA) transistor structures with specific patterning methods, including double-patterning or multi-patterning processes, and the use of dielectric spacers and backside vias to enhance device fabrication, allowing for smaller pitches and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and device reliability becomes difficult to maintain
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (e.g., self-aligned double patterning, self-aligned triple patterning) where each step creates a portion of the final pattern. This segmentation allows complex patterns to be formed through simpler, repeatable steps, managing overall process complexity while achieving high functional density
Solution Approach 2:
Sacrificial layers are formed in advance before the actual device structures are created. These pre-formed sacrificial features guide subsequent patterning steps and enable self-aligned fabrication, reducing the need for complex alignment procedures and maintaining reliability at smaller dimensions
2Area of stationary object
If feature sizes decrease to increase functional density, then chip area utilization improves, but fabrication difficulty increases
Solution Approach 1:
The patent extends fabrication into the vertical dimension by forming three-dimensional structures such as nanosheets, nanowires, and gate-all-around transistors. This allows continued scaling and increased functional density without proportionally increasing lateral fabrication difficulty, as many patterning steps remain similar to planar processes
Solution Approach 2:
Sacrificial layers act as intermediary structures that simplify the fabrication of complex three-dimensional patterns. These temporary features enable self-aligned formation of multiple structures and are removed after serving their guiding function, reducing overall fabrication difficulty
3Ease of manufacture
If traditional planar transistor structures are used, then fabrication is simpler, but device performance and routing flexibility are limited
Solution Approach 1:
The transition from planar to three-dimensional transistor structures (gate-all-around, nanosheet, nanowire) provides additional spatial dimensions for routing and interconnect design. This enables greater routing flexibility and device performance without significantly complicating the core fabrication processes, as the same self-aligned patterning techniques apply
Data Source
AI summary
A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.