Backside Via GAA Source/Drain Wraparound Contacts for Lower Resistance

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Solution Overview

Problem

GAA transistors with backside vias suffer from increased contact resistance due to low-temperature formation of backside silicide regions, which can damage front-end-of-line devices, and existing interconnect techniques are not satisfactory for scaling down integrated circuit footprints.

Innovation Solution

Implementing full-wraparound source/drain contacts that encase all sides of epitaxial source/drain regions, reducing contact resistance with backside vias by using a method that includes forming a sacrificial layer, patterning fin structures, and creating gate-all-around transistors with backside metal vias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If backside silicide regions are formed at low temperature to prevent damage to front-end-of-line devices, then device damage is avoided, but contact resistance increases

Engineering Contradiction:
Improvedevice damageVSAvoidcontact resistance
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The contact structure is segmented into multiple components: a backside via extending through the substrate, a silicide region formed on the backside surface, and a wraparound contact that extends from the front surface through the sidewalls to the backside surface. This segmentation allows the silicide region to be formed at low temperature on the backside while the wraparound contact provides additional low-resistance pathways through the sidewalls, effectively reducing overall contact resistance without causing damage to front-end devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The contact structure transitions from a traditional planar contact to a three-dimensional wraparound configuration. The wraparound contact extends through the sidewalls of the semiconductor structure, adding vertical and lateral dimensions to the contact pathway. This dimensional change creates multiple parallel conduction paths that reduce contact resistance while allowing low-temperature processing to protect front-end devices.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional interconnect techniques are used, then manufacturing is simpler, but integration density cannot be scaled down

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidintegration density
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The invention utilizes the backside surface and sidewalls of the semiconductor structure to create vertical interconnects that extend through the substrate. This three-dimensional approach to interconnection allows multiple contacts to be formed in a compact footprint, enabling scaling of integration density while maintaining manufacturing feasibility through established deposition and etching processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The wraparound contact is nested within the sidewalls of the semiconductor structure, with the contact material conformally coating the vertical surfaces. This nested configuration maximizes the use of available space, allowing multiple such structures to be packed closely together, thereby increasing integration density without requiring proportionally larger manufacturing complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Reliability

If full-wraparound source/drain contacts are implemented, then contact resistance is reduced, but device complexity increases

Engineering Contradiction:
Improvecontact resistanceVSAvoidcontact structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The complex wraparound contact is segmented into discrete processing steps: formation of the via hole through the substrate, deposition of the wraparound contact material conformally on the sidewalls, and planarization to expose the backside surface. This segmentation of the manufacturing process makes the complex three-dimensional structure achievable using standard semiconductor fabrication techniques, reducing the practical complexity despite the advanced geometry.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250359242A1Semiconductor device with backside via
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250359242A1 patent drawing
  • US20250359242A1 patent drawing
  • US20250359242A1 patent drawing

AI summary

A method includes following steps. A bottom sacrificial layer is over a substrate. An epitaxial structure is formed over the bottom sacrificial layer. The epitaxial structure is etched such that the bottom sacrificial layer is exposed. An epitaxial source/drain region is formed on the exposed bottom sacrificial layer. The bottom sacrificial layer is removed from a bottom surface of the epitaxial source/drain region. After removing the bottom sacrificial layer, a source/drain contact is formed wrapping around the bottom surface, a top surface, and opposite sidewalls of the epitaxial source/drain region.