Backside Conductive Vias for Dense Gate-All-Around Transistors
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Solution Overview
Problem
The challenge in integrated circuits is to effectively form dense arrays of gate all around transistors while preventing over-etching, which can damage the transistors and hinder the reduction of feature sizes in integrated circuits.
Innovation Solution
The solution involves forming gate all around transistors in a first wafer over a semiconductor substrate with an etch-stop layer, flipping the wafer, and creating conductive backside vias to connect with the source and drain regions. A second wafer with electronic circuitry is then bonded to the first wafer, ensuring electrical connection and protecting the transistors from over-etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thin-film deposition techniques and etching techniques are used to decrease feature size, then the number of transistors per area increases, but the risk of over-etching increases which can damage transistors
Solution Approach 1:
An etch-stop layer is formed between the substrate and the transistor structure before transistor fabrication. This preliminary protective layer prevents over-etching from damaging the substrate or underlying structures during subsequent etching processes, allowing precise feature formation while maintaining transistor integrity.
Solution Approach 2:
The etch-stop layer acts as an intermediary protective barrier between the etching process and the substrate/transistor structures. This intermediate layer absorbs the harmful effect of over-etching, preventing direct damage to the transistors while allowing the etching process to proceed with high precision.
2Productivity
If the number of transistors is increased for a given area, then computing power increases, but the complexity of forming and protecting each transistor increases
Solution Approach 1:
The substrate structure is segmented into distinct layers including the substrate, etch-stop layer, and transistor structures. This segmentation allows each layer to serve a specific function and simplifies the fabrication process by enabling standardized formation steps that can be replicated across the entire substrate, thereby increasing transistor density while managing complexity.
Solution Approach 2:
The etch-stop layer serves multiple functions: it prevents over-etching damage, provides a defined interface for transistor formation, and enables consistent processing across the entire substrate. This multi-functionality reduces the overall complexity of transistor formation by consolidating protective and structural roles into a single layer.
3Quantity of substance
If memory cell size is reduced to increase memory array density, then storage capacity increases, but it becomes difficult to form effective memory cells
Solution Approach 1:
The etch-stop layer is formed prior to memory cell fabrication, establishing a precise stopping point for etching processes. This preliminary structure enables the formation of smaller memory cells with well-defined dimensions, as the etch-stop layer ensures consistent etch depth and prevents variability that would otherwise limit further size reduction.
Data Source
AI summary
An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.