Backside Via Structure for Low-Drop GAA Transistor Power Delivery
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in scaling down integrated circuits due to increased voltage drop across power rails and power consumption, which are exacerbated by the stacked-up construction of transistors and interconnects, leading to inefficiencies in connectivity and device performance.
Innovation Solution
The implementation of backside metallization and vias in semiconductor devices, which allows for power rails on the backside of the structure, enhancing connectivity and reducing voltage drop by providing additional metal tracks and increasing gate density, while mitigating issues such as unwanted etching and gap fill challenges during via formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional stacked-up construction with transistors and interconnects is used, then device integration is achieved, but voltage drop across power rails increases and power consumption increases
Solution Approach 1:
The patent introduces backside vias that extend through the substrate from the front surface to the back surface, adding a vertical dimension to power delivery. This allows power rails to be routed on both the front and back surfaces of the device, effectively creating a three-dimensional power distribution network that reduces voltage drop by providing additional current paths without increasing planar complexity.
2Productivity
If scaling down semiconductor IC dimensions is performed, then production efficiency improves and costs decrease, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the power delivery function into multiple segments: front surface power rails, backside power rails, and connecting backside vias. This segmentation allows each component to be optimized independently and integrated into existing manufacturing workflows, achieving enhanced performance without proportionally increasing overall process complexity.
3Reliability
If backside metallization and vias are implemented, then connectivity is enhanced and voltage drop is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms backside vias through the substrate before completing the front surface interconnect structure. This preliminary action allows the via holes to be prepared and partially filled in advance, enabling subsequent metallization layers to be deposited and patterned without requiring complex post-processing steps, thereby reducing overall manufacturing complexity despite the added functionality.
Data Source
AI summary
Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.