Backside Voltage Regulator Layout for ASIC Power and Heat Loss
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Solution Overview
Problem
As ASIC dies increase in processing speed, they consume more power, leading to increased heat and potential failure due to copper losses and electromigration, affecting performance and reliability.
Innovation Solution
Integrate an integrated voltage regulator die onto the backside of the ASIC package, utilizing through-silicon vias and a redistribution layer to deliver power efficiently, and include deep trench capacitors and inductors to manage power distribution and reduce copper losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ASIC die processing speed is increased, then processing performance is improved, but power consumption increases leading to heat generation and reliability degradation
Solution Approach 1:
The patent moves the voltage regulator from the traditional front-side power delivery path to the backside of the ASIC die, creating a separate power management dimension. This spatial reconfiguration allows the regulator to be closer to the heat source, enabling more efficient thermal management while maintaining high-speed processing capability.
Solution Approach 2:
The patent introduces an integrated voltage regulator die as an intermediary component between the power source and the ASIC die. This regulator acts as a mediator that can dynamically control power delivery, reducing unnecessary power consumption and heat generation while maintaining the required processing performance.
2Loss of energy
If power delivery distance is reduced, then copper losses are minimized, but package structure complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by placing the voltage regulator on the backside of the ASIC die, effectively reducing the horizontal power delivery distance. This three-dimensional power distribution architecture minimizes copper losses by shortening the current path while the standardized backside integration process manages the structural complexity.
Solution Approach 2:
The patent merges the voltage regulator function with the ASIC die structure by integrating it onto the backside, creating a unified power management solution. This integration combines multiple functions (power regulation, thermal management, and signal distribution) into a single compact structure, reducing overall package complexity despite the increased functional density.
3Temperature
If voltage regulator is integrated closer to heat source, then thermal management is improved, but manufacturing complexity increases
Solution Approach 1:
The patent exploits the backside of the ASIC die as an additional manufacturing dimension, placing the voltage regulator in close proximity to the heat-generating logic circuits. This spatial arrangement enables efficient heat sinking and thermal management while the regulator can be integrated using standard semiconductor fabrication processes, balancing thermal performance with manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated voltage regulator die limits power draw, reduces copper losses, minimizes heat generation, and enhances processing performance by maintaining stable power supply and reducing signal loss, thereby improving the reliability and efficiency of the ASIC package.
Implementation Method 1
utilizing through-silicon vias and a redistribution layer to deliver power efficiently
Implementation Method 2
include deep trench capacitors and inductors to manage power distribution
Implementation Method 3
include deep trench capacitors and inductors to manage power distribution
Implementation Method 4
The integrated voltage regulator die limits power draw, reduces copper losses, minimizes heat generation, and enhances processing performance by maintaining stable power supply
Data Source
AI summary
The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.