Backside Wafer Integration for Compact 3D Semiconductor Stacks
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Solution Overview
Problem
Existing 3D integration processes, including both conventional and sequential methods, fail to maximize area efficiency in semiconductor chip stacking due to limitations in device layer spacing and via height, necessitating further improvements.
Innovation Solution
A sequential integration process is introduced where the backside of a wafer is utilized for device integration, allowing for the formation of a vertical wafer stack with both front and backside device regions, enabling hetero-integration of different semiconductor materials and reducing the overall stack height through the use of group III-V semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional chip-stacking is used, then device layer spacing and via height are reduced, but area efficiency is not maximized
Solution Approach 1:
The patent utilizes the backside of the first wafer to form a second device region, effectively adding another dimension to the device integration space. This allows circuits to be formed on both the front and back sides of the same wafer, thereby improving area efficiency without significantly increasing stack complexity.
2Area of moving object
If sequential integration is used, then device layer spacing is reduced, but area efficiency still needs improvement
Solution Approach 1:
The patent segments the wafer into two separate device regions: a first device region on the front side and a second device region on the back side. This segmentation allows independent processing and optimization of each device region, improving manufacturing precision while maximizing area efficiency by utilizing both sides of the wafer.
3Productivity
If backside of first wafer is utilized, then area efficiency is improved, but processing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the second device region on the backside of the first wafer before finalizing the stack structure. This allows the integration process to be streamlined, as the backside device region is already prepared and can be directly connected to subsequent layers, thereby improving productivity without significantly increasing overall process complexity.
Data Source
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AI summary
According to the present inventive concept there is provided a sequential integration process comprising: forming a wafer stack by bonding a first wafer (210) to a second wafer (220) with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region (212) formed on the front side of the first wafer and including a set of semiconductor devices, subsequent to forming the wafer stack, forming a second device region (232) on a back side of the first wafer, the second device region including a set of semiconductor devices, forming at least one interconnection layer (234) on the second device region for electrically interconnecting the semiconductor devices of the second device region, and forming at least one via (240) extending through the wafer stack from the at least one interconnection layer (234) and through the first wafer (210).