Backside Wafer Dopant Activation at Low Temperature
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Solution Overview
Problem
Existing methods for backside wafer dopant activation in IGBT devices face challenges in controlling doping concentrations and activating implanted impurities at low temperatures to prevent damage to front-side structures, particularly due to the limited activation of boron impurities at low-temperature annealing processes.
Innovation Solution
A low-temperature or room-temperature ion implantation process is performed on the backside of the substrate, followed by a second ion implant to form a collector layer, utilizing a high boron dose and vacancy engineering to generate sufficient vacancy density, thereby eliminating the need for expensive laser annealing tools and improving amorphous layer quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-temperature annealing (around 450°C) is used to prevent aluminum spiking, then front-side structures are protected, but only a small fraction of implanted boron impurities are activated
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature annealing (>700°C) to low-temperature annealing (400-450°C), and combines it with ion implantation to achieve dopant activation while preventing aluminum spiking. This parameter change resolves the contradiction by finding an optimal temperature window that satisfies both protection and activation requirements
Solution Approach 2:
The patent introduces ion implantation as an intermediary process between wafer fabrication and annealing. The ion implantation pre-activates the dopants at low temperature, serving as a mediator that enables dopant activation without requiring high-temperature annealing that would cause aluminum spiking
2Manufacturing precision
If high-temperature annealing is used to activate boron impurities, then dopant activation is improved, but aluminum metal layers spike into adjacent silicon damaging front-side structures
Solution Approach 1:
The patent fundamentally changes the temperature parameter from high-temperature annealing (>700°C) to low-temperature annealing (400-450°C) combined with ion implantation. This parameter change eliminates the harmful aluminum spiking effect while maintaining effective dopant activation through the ion implantation pre-activation mechanism
Solution Approach 2:
The patent converts the limitation of low-temperature annealing (insufficient dopant activation) into a benefit by combining it with ion implantation. The ion implantation process provides the necessary activation energy without thermal damage, turning what was previously a harmful constraint into a useful dual-process approach
3Ease of manufacture
If conventional doping methods are used, then doping process is simple, but doping concentrations in P+ wafers are not well controlled
Solution Approach 1:
The patent replaces the conventional thermal diffusion doping method with ion implantation. Ion implantation provides precise control over dopant concentration and depth through controlled ion beam parameters, substituting the less controllable thermal diffusion process with a more precise physical implantation method
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively activates dopants without damaging front-side structures, achieving efficient dopant activation and reducing end-of-range defects, while maintaining low temperatures to prevent aluminum spiking, thus enhancing IGBT device performance.
Implementation Method 1
performing a low-temperature or room-temperature ion implant to a second main side of the substrate
Implementation Method 2
utilizing a high boron dose and vacancy engineering to generate sufficient vacancy density
Implementation Method 3
performing a low-temperature or room-temperature ion implant to a second main side of the substrate... effectively activates dopants without damaging front-side structures
Data Source
AI summary
Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.