Backside Wafer Etching for Precise Planar Photonics Alignment
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Solution Overview
Problem
The implementation of planar photonics circuits on semiconductor chips requires accurate alignment and removal of silicon substrate portions, which is challenging due to mechanical integrity issues and limited precision in chip-by-chip processing, leading to reduced yield and alignment tolerances.
Innovation Solution
A method involving wafer-level processing to remove specified portions of the silicon substrate while the chips are still part of the intact wafer, using backside etching and patterning techniques to create alignment features and enhance mechanical integrity, allowing for precise alignment and integration of photonic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If chip-by-chip processing is used to remove silicon substrate portions, then alignment can be performed, but mechanical integrity is compromised and precision is reduced
Solution Approach 1:
The patent applies preliminary action by performing backside etching and creating alignment features on the intact wafer before singulation. The alignment features are formed while the wafer maintains its mechanical strength, and then the wafer is singulated to produce individual chips with pre-formed alignment structures, eliminating the need for post-singulation alignment operations that would compromise mechanical integrity.
Solution Approach 2:
The patent segments the processing into distinct stages: (1) backside etching and alignment feature formation on the intact wafer, (2) singulation to separate chips, and (3) subsequent frontside processing. This segmentation allows alignment features to be created when the wafer has full mechanical support, while still enabling precise alignment operations on individual chips after separation.
2Manufacturing precision
If backside etching is performed on intact wafer, then alignment accuracy and mechanical robustness improve, but process complexity increases
Solution Approach 1:
The patent merges multiple functions into the backside etching process: (1) creating physical alignment features that enhance alignment accuracy, (2) improving mechanical robustness by removing problematic substrate portions before singulation, and (3) establishing reference structures for subsequent processing. By combining these functions into a single integrated process step performed on the intact wafer, the patent achieves multiple benefits without proportionally increasing overall process complexity.
3Productivity
If chip-by-chip processing is used, then individual chip processing is possible, but yield is reduced and alignment tolerances are compromised
Solution Approach 1:
The patent performs preliminary alignment feature formation on the intact wafer before singulation, ensuring that all chips inherit precise alignment structures. This preliminary action establishes uniform alignment references across all chips in the wafer, enabling consistent alignment tolerances and improving overall yield by reducing variability between individual chip processing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves chip yield, alignment accuracy, and mechanical robustness, enabling better integration of photonic devices and optical access, while reducing the complexity and cost of subsequent packaging processes.
Implementation Method 1
applying a photoresist material to the backside of the semiconductor wafer. The method also includes exposing particular regions of the backside of the semiconductor wafer through the photoresist material.
Implementation Method 2
The method also includes etching the backside of the semiconductor wafer at the particular regions to form alignment features within the backside of the semiconductor wafer.
Data Source
AI summary
A photoresist material is deposited, patterned, and developed on a backside of a wafer to expose specific regions on the backside of chips for etching. These specific regions are etched to form etched regions through the backside of the chips to a specified depth within the chips. The specified depth may correspond to an etch stop material. Etching of the backside of the wafer can also be done along the chip kerf regions to reduce stress during singulation/dicing of individual chips from the wafer. Etching of the backside of the chips can be done with the chips still part of the intact wafer. Or, the wafer having the pattered and developed photoresist on its backside can be singulated/diced before etching through the backside of the individual chips. The etched region(s) formed through the backside of a chip can be used for attachment of optical component(s) to the chip.