Backside Wafer Thinning for Compact Power Rail Contacts
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Solution Overview
Problem
The semiconductor industry faces challenges in connecting semiconductors to power rails efficiently, requiring significant cell area and impacting circuit integration and uniformity, particularly with finFETs and hGAA structures.
Innovation Solution
A method involving forming an etch stop layer, epitaxial layer, and wafer device on a substrate, followed by grinding and planarization to reduce substrate thickness, and forming contacts to source/drain regions, enabling efficient connection to power rails with reduced cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rail connections are made on the front of the cell, then electrical connection is achieved, but cell area is significantly increased
Solution Approach 1:
The patent inverts the conventional approach by moving power rail connections from the front of the cell to the back of the cell. This is achieved through wafer bonding and thinning processes that enable backside access to power rails, thereby reducing the cell area occupied by front-side connections while maintaining reliable electrical connection.
2Productivity
If substrate thickness is reduced through grinding and planarization, then device integration is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming an etch stop layer at a predetermined depth before the thinning process. This etch stop layer serves as a reference point that guides the grinding and planarization processes, ensuring consistent substrate thickness while simplifying process control. The etch stop layer is formed in advance to prevent over-thinning and to provide a stopping criterion for the thickness reduction processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for more compact semiconductor device design by minimizing the area required for power rail connections, enhancing circuit integration and uniformity while reducing parasitic capacitance and off-state leakage.
Implementation Method 1
grinding the substrate to form a substrate having a second thickness less than the first thickness
Implementation Method 2
planarizing the substrate to form a substrate having a third thickness less than the second thickness
Implementation Method 3
removing the etch stop layer to expose a source/drain region on the wafer device
Data Source
AI summary
A method of forming a semiconductor device is provided. The method includes forming an etch stop layer on a substrate having a first thickness, forming an epitaxial layer on the etch stop layer, and forming a wafer device on the epitaxial layer. The wafer device is bonded to a bonding wafer using hybrid bonding. The substrate is then ground to a second thickness less than the first thickness and planarized to a third thickness less than the second thickness. A mask layer is deposited on a bottom surface of the etch stop layer, and at least one via opening is formed in the mask layer. The etch stop layer is selectively removed, and the mask layer is removed to expose the substrate at the third thickness.