Backside Wire Routing Through Deep Vias in Dense Semiconductor Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing density of semiconductor devices poses challenges in providing electrical connections and signal line routing due to spatial and electrical constraints, limiting the availability of space for wiring and routing resources.
Innovation Solution
Employing backside wires and deep vias to create electrical pathways between the frontside and backside of semiconductor devices, allowing for additional wiring options without displacing existing components, including the use of local interconnects and deep vias that traverse FEOL structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional frontside-only wiring is used, then routing is simple, but wiring options are limited and areal density increases
Solution Approach 1:
The patent utilizes the backside of the semiconductor device as a third dimension for routing, transitioning from traditional planar (2D) frontside-only wiring to three-dimensional (3D) wiring that includes backside interconnect layers. This allows signals to be routed on the backside of the device, effectively adding a new dimension to the routing space and increasing wiring options without increasing the chip footprint area.
Solution Approach 2:
The patent implements deep vias that extend through FEOL structures to connect frontside contacts to backside interconnect layers. This nesting approach allows multiple routing layers to be stacked vertically, with frontside and backside wiring layers nested together through the device thickness, maximizing the use of available 3D space for routing.
2Adaptability or versatility
If more wiring layers are added to increase routing options, then adaptability improves, but device complexity increases
Solution Approach 1:
The patent divides the wiring structure into distinct frontside and backside interconnect layers, with deep vias providing controlled connections between them. This segmentation allows independent optimization of frontside and backside routing, simplifying the design and fabrication process compared to a fully integrated multi-layer structure, while still providing enhanced routing flexibility.
3Adaptability or versatility
If deep vias are used to connect frontside to backside, then wiring options increase, but manufacturing complexity increases
Solution Approach 1:
The patent forms deep vias through FEOL structures before completing the backside interconnect layer formation. This preliminary action allows the deep via locations and paths to be predetermined and established early in the fabrication process, simplifying subsequent backside wiring implementation and reducing overall manufacturing complexity despite the added 3D routing capability.
Data Source
AI summary
A semiconductor device includes an electrical pathway connecting a frontside of the semiconductor device to a backside of the semiconductor device. The electrical pathway includes a backside wire disposed within a backside interconnect layer. A first deep via connects to the backside wire, the first deep via extending through a front end of line (FEOL) region. A local interconnect connects to and extends transversely to the first deep via to connect the backside wire to a frontside component.