Backside Wiring Layout for Dense Standard Cell Routing

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Solution Overview

Problem

The increasing complexity of integrated circuits due to miniaturization and reduced power supply voltage leads to significant parasitic effects from wiring, necessitating improved methods for arranging interconnecting lines to enhance routing efficiency and reduce power loss.

Innovation Solution

The integration of a backside wiring pattern on a substrate with internal connection nodes and gate lines, along with frontside and backside contacts, allows for increased routing freedom and reduced complexity, enabling efficient signal transmission and power distribution within the integrated circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the width, gap space, and height of wires are reduced to increase integration density, then the degree of integration is improved, but the parasitic element of the wiring increases

Engineering Contradiction:
Improveintegration densityVSAvoidparasitic element
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a backside wiring layer on the opposite side of the substrate from the frontside wiring layer, effectively moving the wiring solution to another dimension (the third dimension through substrate thickness). This allows power and ground signals to be routed on the backside, separating them from the frontside signal wiring, thereby reducing parasitic coupling and interference while maintaining high integration density on the frontside.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the size of the standard cell is reduced to increase cell density, then the integration density is improved, but the complexity of arranging interconnecting lines increases

Engineering Contradiction:
Improvecell densityVSAvoidarrangement complexity of interconnecting lines
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

By utilizing the backside of the substrate for wiring, the patent effectively adds a vertical dimension to the routing space. This allows interconnecting lines to be arranged more freely without being constrained to the two-dimensional plane of the frontside, thereby reducing arrangement complexity even as cell density increases.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the wiring function into two separate layers: frontside wiring for signal transmission and backside wiring for power and ground distribution. This segmentation allows each layer to be optimized independently, simplifying the arrangement of interconnecting lines while maintaining high cell density.

Inventive Principle:
Principle #1Segmentation

3Use of energy by moving object

If the voltage of the power supply is reduced to decrease power consumption, then power consumption is reduced, but the influence of parasitic elements on the integrated circuit increases

Engineering Contradiction:
Improvepower consumptionVSAvoidparasitic element influence
Core Design Contradiction:
Use of energy by moving objectVSObject-generated harmful factors

Solution Approach 1:

The backside wiring layer provides a dedicated path for power and ground signals, physically separating them from signal wiring on the frontside. This separation reduces parasitic coupling and interference, allowing the circuit to operate reliably at lower voltages where parasitic effects would otherwise be more significant.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The backside wiring layer acts as an intermediary structure that mediates between the power supply and the frontside circuitry. By providing a low-impedance power and ground distribution network on the backside, it reduces the impact of parasitic elements on signal integrity, enabling lower operating voltages.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240266290A1Integrated circuit including backside wiring pattern
Publication Date: 2024.08.08 SAMSUNG ELECTRONICS CO LTD
  • US20240266290A1 patent drawing
  • US20240266290A1 patent drawing
  • US20240266290A1 patent drawing

AI summary

An integrated circuit includes a substrate and a plurality of standard cells on the substrate. A standard cell of the plurality of standard cells includes a backside wiring pattern arranged on a lower portion of the substrate and including at least an internal connection node of the standard cell and a plurality of gate lines arranged on an upper portion of the substrate and extending in a first horizontal direction. At least one of the plurality of gate lines functions as an input pin of the standard cell.