Backside Wiring Layout for IC Parasitic Resistance Reduction
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Solution Overview
Problem
Integrated circuits face challenges in achieving high integration and performance due to increased parasitic elements from reduced wiring line widths, spaces, and heights, which affect power supply voltage and operation speed.
Innovation Solution
The integration circuit employs backside wiring with through silicon vias and patterns in the backside wiring layer to route control signals and supply voltages, reducing parasitic resistance and increasing routing resources while maintaining high integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wiring line widths, spaces, and heights are reduced to achieve high integration, then integration density is improved, but parasitic elements increase
Solution Approach 1:
The patent introduces backside wiring layers beneath the substrate, adding a new dimensional space for signal routing. This allows wiring to be distributed across multiple layers (front side and back side), effectively increasing the available routing volume without reducing the dimensions of individual wiring lines, thus maintaining lower parasitic elements while achieving high integration density.
2Use of energy by moving object
If power supply voltage is reduced to decrease power consumption, then power consumption is improved, but the influence of parasitic elements increases
Solution Approach 1:
By distributing wiring across multiple layers including backside wiring, the patent reduces the length of individual wiring paths and provides multiple routing options. This reduces parasitic resistance and capacitance, allowing the circuit to operate reliably at lower power supply voltages with reduced power consumption.
3Speed
If wiring line dimensions are reduced to increase operation speed, then integration is improved, but parasitic elements increase affecting performance
Solution Approach 1:
The backside wiring structure provides additional routing dimensions that allow for optimized signal paths. By routing signals through multiple layers including the backside, the patent reduces the effective wiring length and parasitic elements, enabling faster operation speeds while maintaining high integration.
Data Source
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AI summary
Provided is an integrated circuit including a cell region in which a plurality of cells are arranged, and a peripheral region in which a circuit configured to control the plurality of cells is arranged, wherein the cell region further includes a plurality of first gate lines over a substrate, a plurality of first patterns in a first wiring layer above the plurality of first gate lines, a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate, and a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction, wherein each of the plurality of first vias includes a top surface connected to a respective one of the plurality of first patterns and a bottom surface connected to a respective one of the plurality of second patterns.