Back-Side Wiring Layout for Stable IC Power Delivery
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Solution Overview
Problem
Integrated circuits face challenges in maintaining stable and high-performance operation due to the amplification of parasitic components caused by decreasing wire dimensions and power supply voltages, which affect the transmission of voltage to cell arrays.
Innovation Solution
The design of an integrated circuit with a substrate featuring a cell area and a dummy area, including a front-side wiring layer, through vias, and a back-side wiring layer that directly connects to transistors, reducing the path for voltage transmission and minimizing IR drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wire dimensions are decreased to achieve higher integration, then integration density is improved, but parasitic components are amplified
Solution Approach 1:
The patent introduces back-side wiring layers and through-substrate vias to transmit power and ground signals from the rear surface of the substrate to the cell arrays. This three-dimensional wiring approach adds a vertical dimension to signal transmission, effectively separating power delivery paths from the planar front-side signal routing. This dimensional transition reduces the impact of parasitic components by providing alternative current paths and reducing IR drops in the scaled-down wire dimensions.
Solution Approach 2:
The patent introduces dummy areas containing through-substrate vias and back-side wiring as intermediary structures that facilitate voltage transmission from the back-side to the cell arrays. These intermediary elements act as mediators to stabilize voltage delivery and compensate for the increased parasitic effects in reduced-dimension front-side wiring, ensuring stable operation despite scaled-down wire dimensions.
2Use of energy by moving object
If power supply voltage is decreased to reduce power consumption, then power consumption is reduced, but the influence of parasitic components increases
Solution Approach 1:
By transitioning to three-dimensional wiring with back-side power delivery, the patent reduces the effective resistance and inductance in the power supply network. This spatial reconfiguration allows for lower operating voltages by providing more direct and less parasitic-affected current paths to the cell arrays, enabling reduced power consumption without being constrained by parasitic voltage drops.
3Device complexity
If conventional front-side wiring is used without back-side connections, then routing simplicity is maintained, but voltage transmission stability deteriorates
Solution Approach 1:
The patent segments the wiring function into distinct front-side and back-side layers, with the front side handling signal routing and the back side handling power and ground distribution. This functional segmentation allows each layer to be optimized independently - the front side maintains routing simplicity while the back side provides stable voltage transmission through dedicated power delivery networks and through-substrate via connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance and reliability of the integrated circuit by stabilizing voltage transmission to cell arrays, reducing IR drops, and enhancing routing flexibility.
Implementation Method 1
a voltage applied to the back-side wiring layer passes through the plurality of through vias and the front-side wiring layer to at least one transistor included in the plurality of cells
Data Source
AI summary
An integrated circuit includes: a substrate including a cell area and a dummy area, wherein a plurality of cells are arranged in the cell area; a front-side wiring layer arranged over a front surface of the substrate in a vertical direction, wherein the front-side wiring layer includes a first pattern extending in a first direction across the cell area and the dummy area and a second pattern extending in a second direction intersecting the first direction and contacting the first pattern; a through via overlapping the front-side wiring layer in the vertical direction in the dummy area and passing through the substrate; and a back-side wiring layer arranged on a rear surface of the substrate, wherein the back-side wiring layer is connected through the through via and the front-side wiring layer to at least one transistor included in the plurality of cells.