Backside Wiring Layout for Dense IC Routing With Lower Parasitics
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Solution Overview
Problem
Integrated circuits face challenges in achieving high integration and performance due to increased parasitic elements from reduced wiring line widths, spaces, and heights, which affect power supply voltage and operation speed.
Innovation Solution
The integration circuit employs backside wiring with through silicon vias and patterns in a backside wiring layer to route control signals and supply voltages, reducing parasitic resistance and increasing routing resources while maintaining high integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If wiring line widths, spaces, and heights are reduced to achieve high integration, then integration density is improved, but parasitic elements increase causing performance degradation
Solution Approach 1:
The patent introduces a backside wiring layer located beneath the substrate, adding a new dimensional space for routing. This allows wiring to be distributed across both front and back sides of the substrate, effectively increasing the available routing area without increasing the planar footprint, thus maintaining high integration while reducing parasitic effects through optimized current distribution
Solution Approach 2:
The wiring function is segmented between front-side wiring layers and backside wiring layers. The backside wiring layer handles specific routing tasks (such as power supply and control signals), while front-side layers handle other functions. This segmentation allows optimization of each layer's routing independently, reducing parasitic interference and improving overall circuit performance
2Use of energy by moving object
If power supply voltage is reduced to decrease power consumption, then power efficiency is improved, but the influence of parasitic elements on operation speed increases
Solution Approach 1:
The backside wiring layer provides additional routing paths for power supply and control signals, allowing optimization of current distribution. This reduces parasitic resistance in power delivery, enabling efficient operation at lower voltages without sacrificing speed, as the optimized routing compensates for the reduced voltage headroom
3Area of stationary object
If wiring line dimensions are reduced to increase integration, then area efficiency is improved, but routing resources become insufficient
Solution Approach 1:
By utilizing the backside of the substrate for wiring, the patent effectively doubles the available routing area. This provides abundant routing resources for controlling a large number of cells without increasing the planar area of the integrated circuit, as the backside wiring layer serves as an additional routing plane
Solution Approach 2:
The backside wiring layer serves multiple functions including power supply distribution, control signal routing, and inter-cell communication. This multi-functionality maximizes the utility of the available wiring resources, enabling efficient control of numerous cells with limited routing capacity in the planar direction
Data Source
AI summary
Provided is an integrated circuit including a cell region in which a plurality of cells are arranged, and a peripheral region in which a circuit configured to control the plurality of cells is arranged, wherein the cell region further includes a plurality of first gate lines over a substrate, a plurality of first patterns in a first wiring layer above the plurality of first gate lines, a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate, and a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction, wherein each of the plurality of first vias includes a top surface connected to a respective one of the plurality of first patterns and a bottom surface connected to a respective one of the plurality of second patterns.