Backside Wiring Layout for Dense Memory Signal Integrity
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Solution Overview
Problem
Advancements in semiconductor processes lead to increased parasitic elements in integrated circuits due to reduced wire widths and spacings, affecting performance and reliability by causing voltage drops and delayed signal propagation, especially in memory devices with high integration demands.
Innovation Solution
The integration circuit design incorporates backside wires and contacts to reroute supply voltages and signals, reducing parasitic resistance and capacitance by utilizing a backside wiring layer below the substrate and vertical contacts to connect gate and bit lines, thereby enhancing routing resources and minimizing the impact of parasitic elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wire widths and spacings are reduced for high integration, then integration density is improved, but parasitic elements increase causing voltage drops and delayed signal propagation
Solution Approach 1:
The patent introduces a backside wiring layer beneath the substrate to route power supply lines and signals in a third dimension. This allows front-side signal wires to be narrower without increasing parasitic effects, as the power delivery path is separated into a different spatial plane. The backside wiring layer provides low-impedance power paths that do not interfere with the dense front-side signal routing.
2Use of energy by moving object
If power supply voltage is reduced for reduced power consumption, then energy efficiency is improved, but the influence of parasitic components becomes more significant
Solution Approach 1:
By routing power supply lines in a dedicated backside wiring layer, the patent creates low-impedance power paths that are electrically separated from the front-side signal paths. This dimensional separation reduces the impact of parasitic resistance and capacitance on signal integrity, allowing operation at lower voltages without compromising reliability.
3Area of stationary object
If wire dimensions are reduced for high integration, then device density is improved, but parasitic resistance and capacitance increase
Solution Approach 1:
The patent separates power delivery functions into a backside wiring layer, allowing front-side wires to be minimized for high density without bearing the burden of power delivery parasitics. The backside layer provides robust power paths with lower parasitic elements, decoupling the constraints of signal routing from power distribution.
Solution Approach 2:
The patent segments the wiring functions into distinct layers: front-side wires for signal routing and backside wires for power delivery. This segmentation allows each layer to be optimized independently - front-side wires can be narrow for high density while backside wires provide low-impedance power paths, reducing the overall parasitic impact on circuit performance.
Data Source
AI summary
An integrated circuit is provided and includes a memory cell array, a plurality of gate electrodes extending in a first direction above a substrate, a plurality of word lines extending in the first direction above the substrate, a plurality of bit lines extending below the substrate in a second direction intersecting the first direction, and a plurality of first contacts passing through the substrate in a vertical direction and respectively connected to the plurality of bit lines.