Backside Wiring Layout With Power Tap Cells for Parasitic Reduction
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Solution Overview
Problem
As semiconductor processes advance and integration increases, the adverse effects of parasitic elements in wiring on integrated circuits become more significant, particularly with decreasing power supply voltages and increasing operational speeds, necessitating improved methods for routing wirings and vias to enhance area efficiency and performance.
Innovation Solution
The integration of a front wiring layer and a backside wiring layer, with power tap cells disposed in standard cells, allows for reduced routing complexity and enhanced area efficiency by electrically connecting the backside wiring layer with the front wiring layer through vias, thereby improving power distribution and reducing wiring lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If wiring widths and intervals are decreased to achieve higher integration, then integration density is improved, but parasitic elements increase adversely
Solution Approach 1:
The patent introduces a backside wiring layer on the rear surface of the substrate, adding a vertical dimension to the wiring architecture. This allows power and signal routing to occur in three-dimensional space rather than confined to two-dimensional front surface layers, thereby reducing parasitic effects while maintaining high integration density.
Solution Approach 2:
The wiring system is segmented into multiple independent layers: front wiring layers for signal routing and backside wiring layers for power distribution. This segmentation allows optimized routing paths for different functions, reducing interference and parasitic elements between power and signal lines.
2Use of energy by moving object
If power supply voltage is decreased to reduce power consumption, then power efficiency is improved, but the adverse effect of parasitic elements increases
Solution Approach 1:
By routing power lines through the backside wiring layer in addition to front surface layers, the patent creates multiple parallel power distribution paths. This reduces the effective resistance and inductance of power delivery, mitigating parasitic effects even at lower operating voltages where power consumption is reduced.
3Device complexity
If front wiring layer and backside wiring layer are integrated with power tap cells in standard cells, then routing complexity is reduced, but manufacturing complexity increases
Solution Approach 1:
The power tap cell is designed as a universal building block that can be instantiated within standard cells and serves multiple functions: providing power taps, creating vias between front and back wiring layers, and maintaining standard cell dimensional consistency. This multi-functionality simplifies routing design while standardizing the manufacturing process.
Solution Approach 2:
The patent merges the power tap function, via formation, and standard cell structure into a single integrated component. The power tap cell combines through-holes or vias that connect front and back wiring layers with the standard cell geometry, eliminating the need for separate power tap structures and simplifying both routing and manufacturing.
Data Source
AI summary
An integrated circuit includes standard cells on a front surface of a substrate, a front wiring layer extending in a first direction on the front surface of the substrate, and a backside wiring layer disposed on a rear surface of the substrate. A first standard cell of the standard cells includes a first gate line and a second gate line arranged apart from each other in the first direction to each extend in a second direction and power tap cells between the first and second gate lines, the power tap cells include a first power tap cell and a second power tap cell apart from the first power tap cell by a first interval in the first direction, and each of the first and second power tap cells is configured to electrically connect the backside wiring layer with the front wiring layer.