Backtrace Algorithm for Logic Error Localization in Digital Circuits
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Solution Overview
Problem
Integrated circuits face challenges in locating logic errors and manufacturing defects during at-speed functional testing, as conventional methods lack systematic procedures for identifying error sources and distinguishing between logic errors and manufacturing defects.
Innovation Solution
A method that backtraces detected errors to their source within the IC, using assertion-checking circuits and a line justification algorithm to extend the error path, allowing for the identification of input signals causing errors without requiring knowledge of expected values, and iteratively tracing through fanin cones to find the error's origin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If in-system functional testing is performed to detect logic errors and manufacturing defects, then detection capability is improved, but the ability to locate error sources deteriorates due to lack of systematic procedures
Solution Approach 1:
The patent segments the error localization problem by dividing the circuit into fanin cones and processing elements. The backtrace algorithm segments the error path into discrete segments that can be individually analyzed, allowing systematic identification of error sources without requiring complete circuit observation.
Solution Approach 2:
The patent implements preliminary action by pre-configuring wrapper circuits around processing elements that capture and store error information as it propagates through the circuit. This preliminary capture of error states enables subsequent systematic analysis without requiring changes to the normal operational testing procedure.
2Measurement precision
If assertion checking circuits are added to enable error detection, then detection precision is improved, but device complexity increases due to additional hardware
Solution Approach 1:
The wrapper circuits serve multiple functions: they capture error states, store diagnostic information, and enable backtrace analysis. This multi-functionality reduces the need for separate dedicated assertion checking circuits for each processing element, thereby limiting the increase in device complexity while maintaining high detection precision.
Solution Approach 2:
The wrapper circuits are self-configuring and automatically capture error information without requiring external control or additional complex logic. The circuits service themselves by autonomously monitoring their associated processing elements and storing error states, which minimizes the complexity overhead.
3Reliability
If manufacturing testing is performed to detect manufacturing defects, then defect detection is improved, but exhaustiveness deteriorates allowing certain defects to escape detection
Solution Approach 1:
The patent implements feedback by using the backtrace algorithm to trace error manifestations back to their sources, providing information about which manufacturing defects escaped detection. This feedback loop enables identification of testing gaps and allows for enhanced manufacturing test procedures to be developed, progressively improving testing exhaustiveness.
Data Source
AI summary
When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k−1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.